Customer Reviews

Advanced FPGA Design: Architecture, Implementation, and Optimization

5 star:		(14)
4 star:		(1)
3 star:		(0)
2 star:		(1)
1 star:		(0)

 

 

For your convenience, I am publishing errata on my website: [...]

Background on the book:

After having been exposed to a wide variety of designs in a wide range of industries, I began developing my own arsenal of techniques and heuristics from the combined knowledge of these experiences. When mentoring new FPGA design engineers, I draw my suggestions and recommendations from this experience. Up until now, many of these recommendations have referenced specific white papers and application notes (appnotes) that discuss specific practical aspects of FPGA design. The purpose of this book is to condense years of experience spread across numerous companies and teams of engineers, as well as much of the wisdom gathered from technology-specific white papers and appnotes, into a single book that can be used to refine a designer's knowledge and aid in becoming an advanced FPGA designer.

There are a number of books on FPGA design, but few of these truly address advanced real-world topics in detail. This book attempts to cut out the fat of unnecessary theory, speculation on future technologies, and the details of outdated technologies. It is written in a terse, concise format that addresses the various topics without wasting the reader's time. Many sections in this book assume that certain fundamentals are understood, and for the sake of brevity, background information and/or theoretical frameworks are not always covered in detail. Instead, this book covers in-depth topics that have been encountered in real-world designs. In some ways, this book replaces a limited amount of industry experience and access to an experienced mentor and will hopefully prevent the reader from learning a few things the hard way. It is the advanced, practical approach that makes this book unique.

One thing to note about this book is that it will not flow from cover to cover like a novel. For a set of advanced topics that are not intrinsically tied to one another, this type of flow is impossible without blatantly filling it with fluff. Instead, to organize this book, I have ordered the chapters in such a way that they follow a typical design flow. The first chapters discuss architecture, then simulation, then synthesis, then floorplanning, and so on. This is illustrated in the Flowchart of Contents provided at the beginning of the book. To provide accessibility for future reference, the chapters are listed side-by-side with the relevant block in the flow diagram. The remaining chapters in this book are heavy with examples. For brevity, I have selected Verilog as the default HDL (Hardware Description Language). Xilinx as the default FPGA vendor, and Synplicity as the default synthesis and floorplanning tool. Most of the topics covered in this book can easily be mapped to VHDL, Altera, Mentor Graphics, and so forth, but to include all of these for completeness would only serve to cloud the important points. Even if the reader of this book uses these other technologies, this book will still deliver its value. If you have any feedback, good or bad, feel free to email me at the address listed in the preface.

Books on basic logic design swarm the shelves. So do books on Verilog and VHDL. Why, then is logic design always learned on the job? I mean real, industrial logic design, with all the gritty bits. Kilts asked the question too, and wrote this book in response.

The first three chapters start in on the first three goals (conflicting goals, usually) of logic design: high speed, low power, and minimal area. Speed, of course, includes both throughput and latency - again, goals that often conflict with each other. Examples go well beyond the basic, on up to pipelined AES, a pipelined RISC, IEEE floating point units, and commercial standards for digitized audio, case studies with plenty of room to make the design points that Kilts means to get across.

The book's value comes from its willingness to get into technology specifics, way past the bland idealizations of pure logic design. For example, clock gating doesn't just make a design hard to follow, it often blocks the use of the chip's special purpose clock networks. Those have been engineered beyond belief for low skew under massive loading. You can use other wires as clocks, but you expose yourself to lots of ugly problems when you do. Special logic inputs matter, too, especially dedicated set and reset lines on flops. (I've seen some remarkable uses of the dedicated carry lines between closely coupled LUTs, too, but he doesn't touch on those.)

Of course, there are weak spots. Kilts touches on simulation and testbenches, but only touches. Testbenches and verification have their own texts, though, and exotica like mixed level simulations depend intimately on the specific tools at hand. A few pages, but only a few, presented maddening typos, like the capital-X-sub-i on p.125 where small-x-sub-i would have made sense (non-technical readers: if you made it this far, just trust me, it matters), or the resistor symbol in figure 15.12 where inductance is discussed. Section 8.2, on implementing math.h kinds of functions should simply have been dropped, or maybe replaced with a discussion on range reduction. The intended reader took Calc I and remembers the Taylor expansion. Being familiar is its only advantage, though. It doesn't minimize mean-square or maximum error, doesn't deal with endpoint continuity or differentiability in piecewise approximations (which aren't mentioned either), and has lots more problems. A list of grown-up techniques and references would have been far more helpful. Also, this text simply does not address one of the most pressing and painful issues in real-world logic design: compilation time. Although Kilts mentions floor-planning, he says nothing about how it supports incremental compilation, and notes tradeoff of result quality vs. turnaround in only one offhand phrase, as near as I could tell. Incremental compilation might be a non-Xilinx advantage, though, so forgivable within Kilts's stated limitations.

Kilts more than makes up for that small weakness in other areas, including discussion of parameterization. Because this is Verilog based, it doesn't mention VHDL's architecture configurability. Even in Verilog, though, parameterization appears pervasively in industrial design, especially when reuse matters, and rarely if ever shows its face in basic texts on logic design.

This book assumes that you already know Verilog well enough to build a simple pipelined processor, or at least to follow along closely. It also assumes that you've spent some time with industrial synthesis tools, and can translate from tool-specific advice in this book into the different but equivalent specifics of the tools that you're using. In academic terms, I'd call it a backup text for a third course in logic design, or for a course in something else that uses FPGAs heavily. It's not just for classrooms, though. Beginning professionals stand to benefit from this advice, and even battle-scarred logic designers who still remember 5V power rails might pick up a hint or two.

-- wiredweird

This is a great reference book for any level FPGA designer. This book skips past the basics unlike most books on FPGA design and jumps right into advanced topics that practical FPGA designers need to be aware of.

Plenty of discussion on the trade offs that must be faced in FPGA design based on you desired optimization target (speed, size, & power) and discussion of methods to achieve that goal. Lots of practical example code is used to illustrate each topic.

Discussion of simulation techniques and coverage which is becoming a key factor in verifying HDL based designs.

This book contains several topics that I have been waiting to see discussed well in a textbook including floorplanning and the pitfall of using asynchronous resets.

Besides HDL design techniques, the author discusses the PCB level design methodologies that must be used when designing an FPGA into a system. This disscussion is a great complement to this already fine book.

I felt the author was well versed in real-world FPGA design. This book doesn't discuss any of the basics, but does an excellent job in explaining topics such as architecting for speed, synthesis, and place and route optimization, etc. This is the most useful FPGA book that I've read.

This is an excellent book that covers many key points often only learned after many projects. The book covers topics such as multiple clock domains, reset strategies and optimizing for speed, power, or area.
There are many Verilog examples to illustrate key points as well, but techniques also can be applied to VHDL.

Finally! A book that actually talks about advanced design techniques instead of giving a historical overview of FPGA design.

I have to admit that I didn't read this book cover to cover. Rather, I use it for reference as needed. It's starting to get that same tabbed look that my other reference books have.

I had really high hopes for this book based on the other reviews, but found it to be lacking.
Doing FPGA design for a living I'm more than happy to spend $90 on any book that can teach me something new and useful.
Unfortunately that didn't happen with this one.
The book gives a good overview of the design process and tool flow. It also looks at some of the design mistakes a beginner might make. However having the word "Advanced" in the title made me hope for something more substantial...
My recommendation for anyone with more than a couple of years of design experience with FPGAs is to read the Xilinx and Altera white papers and tool manuals instead.
The latter in particular can be arduous reading, but they're full of relevant information.

If you're anything like me, you probably started doing FPGA design because it needed to be done and there wasn't anybody else to do it. It probably took you awhile to get up to speed, and you probably don't feel like you're a 'master.' Your design style probably evolved over time based on frustrating hours spent figuring out why your synthesis tool wouldn't accept what you thought was perfectly good HDL.

There are a lot of little "tricks" that I figured out along the way, such as the fact that including reset functionality in a state machine isn't all that useful most of the time, and often adds a significant cost in gate count.

Kilts hits on a lot of things in this book that I've had to figure out on my own the hard way, which makes it an invaluable reference to the practicing hardware engineer.

He takes the time to describe a lot of ideas that were never clearly explained to me anyplace else, such as how clock transport delay 'races' logic propagation delay in many designs, or why it's often better in an FPGA design to use a fast clock with an enable rather than a clock divider to drive flip-flops in your data path, even though clock dividers are more elegant from a purely HDL perspective.

Overall, the book is a very valuable resource and I have learned a lot from it. In particular the chapters on synthesis and place-and-route were very useful, and contained information that is hard to find (like what the 'register balancing' synthesis option actually does).

The only thing I don't like about this book is the sample designs. The book devotes a chapter each to four different sample designs, but they're not as fleshed out as I would need them to be in order to get any real use out of them. For example, the sample design of the SPDIF decoder was useless for me. I've never studied SPDIF and the author doesn't really explain how the format works so it was hard for me to understand what was going on in the reference design. I wish that the author had taken the time to explain _what_ he was implementing in the sample designs, and maybe spend some time talking about what happens in his Verilog during each stage of the data path.

Finally, this book assumes some experience - you will not learn Verilog syntax from this book nor will it teach you how to "think" in HDL. You won't be able to follow what Kilts is talking about most of the time unless you've already completed a few reasonably complex FPGA designs. However, if you're like me and you already have enough knowledge to be dangerous but there are some gaps in your expertise, you will find this book a very good read.

Very good book, expecially for the advices presents in it, unfortunately for some implementation aspects, the author, focuses too much on the Verilog language.

Early on in design and avoid many more in the lab by buying this book. I remember upon first read, I was expecting a text heavy on HDL syntax and Tool flow. Indeed there are several HDL coding examples and Tool direction hints, but most impressive is the detail taken in regard to practical issues in relation to clocking considerations, up-front design architecture, and other areas which require careful construction toward an FPGA functioning as intended.