Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime®, Second Edition describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is covered in detail. The emphasis of this book is on real-time application of Synopsys tools, used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, sub-micron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, physical synthesis, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-around described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basis of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solution. Target audiences for this book are practicing ASIC design engineers and masters level students undertaking advanced VLSI courses on ASIC chip design and DFT techniques.
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Most Helpful Customer Reviews
3 of 3 people found the following review helpful:
4.0 out of 5 stars
hands on guide,
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This review is from: Advanced ASIC Chip Synthesis Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime® (Hardcover)
This book is geared towards the synopsys synthesis tools (as evident in the title). It gives brief explanations about vhdl and verilog coding style (which can be found in many other books).The actual useful part was that the book explored the commonly used synthesis commands in synopsys, and also had explanations on the steps to follow to succesfully synthesize rtl. These ideas can also be used on synthesis tools from other vendors. This book is good for people already familiar with front end rtl design and are looking into moving to backend.
3 of 6 people found the following review helpful:
3.0 out of 5 stars
ok for an introduction to the tools,
By A Customer
This review is from: Advanced ASIC Chip Synthesis Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime® (Hardcover)
This book is interesting as an introduction to these tools but needs more depth
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Inside This Book
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First Sentence:
As deep sub-micron semiconductor geometries shrink, traditional methods of chip design have become increasingly difficult. Read the first page Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
clock network delay, structured netlist, inserted netlist, total negative slack, physical compiler, destination flop, list clk, physical placement information, clock latency, clock tree insertion, normal flops, sdf file, data required time, tck trst, clock tck, scan insertion, floorplan information, input transition time, drive strength gates, verilog format, delay calculator, verilog netlist, modified netlist, data arrival time, original netlist Key Phrases - Capitalized Phrases (CAPs): (learn more)
Design Compiler, Tue Nov, Path Type, Point Incr Path, Register Transfer Level New!
Books on Related Topics | Concordance | Text Stats Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Index | Back Cover | Surprise Me!
As deep sub-micron semiconductor geometries shrink, traditional methods of chip design have become increasingly difficult. Read the first page Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
clock network delay, structured netlist, inserted netlist, total negative slack, physical compiler, destination flop, list clk, physical placement information, clock latency, clock tree insertion, normal flops, sdf file, data required time, tck trst, clock tck, scan insertion, floorplan information, input transition time, drive strength gates, verilog format, delay calculator, verilog netlist, modified netlist, data arrival time, original netlist Key Phrases - Capitalized Phrases (CAPs): (learn more)
Design Compiler, Tue Nov, Path Type, Point Incr Path, Register Transfer Level New!
Books on Related Topics | Concordance | Text Stats Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Index | Back Cover | Surprise Me!
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