Covering the material in Version 5.0 and significant additions and changes necessitated by the evolution of the architecture since the writing of the first edition. The significant technical changes include clarification of Mxx FPCT operand and Trap Disable Flags, clarification of system architecture and programming implications, and the addition of aCVTST, WMB, EXCB instructions.
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Editorial Reviews
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The third edition reflects the latest implementations of the architecture, including the 21164A, 21164PC, and 21264. Some of the extensions to the architecture and the enhancement to the technical content include: new byte and word load, store and sign-extend operations; new multimedia instructions; new population enumeration and floating-point square root instructions; new instructions to improve data cache efficiency and updated Windows NT section.The Alpha chip is the fastest chip on the marketplace today. It runs Windows NT, UNIX and OpenVMS operating systems. New base-level server configurations provide four times the memory of current systems.
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About the Author
The Alpha Architecture Committee represents all the disciplines of computer engineering at Digital Equipment Corporation.
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5 of 5 people found the following review helpful:
5.0 out of 5 stars
Alpha Architecture Manual -- Great stuff!,
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This review is from: Alpha Architecture Reference Manual, Third Edition (HP Technologies) (Paperback)
I've been an Alpha developer for the NetBSD Operating System Project for several years now, and simply can't say enough about this book. It, like most documentation from Digital (now Compaq), is very thorough and well organized. It is a must for anyone doing systems programming on the Alpha, and quite valuable for people doing application optimization, as well.It discusses the OpenVMS, Digital UNIX, and Windows NT PALcode operations in detail, has a full instruction set reference, discussions on performance optimizations, and also describes other architectural details, such as the console software interface. If you're not an Alpha developer, get it anyway! The design decisions are discussed in detail, and it's a great way to learn about modern, high performance architecture design.
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First Sentence:
Alpha is a 64-bit load/store RISC architecture that is designed with particular emphasis on the three elements that most affect performance: clock speed, multiple instruction issue, and multiple processors. Read the first page Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
longword queue, illegal operand exception, processor issue sequence, translation buffer invalidate, secondary interlock, service routine entry point, logout area, octaword aligned, interlocked resident, memory management fault, primary bootstrap image, underflow enable, asynchronous system traps, invalid operation trap, kernel stack pointer, privileged context block, arithmetic trap, internal processor register, swap privileged context, interlocked insertions, software interrupt level, restart parameter block, system cycle counter, unused function codes, quadword aligned Key Phrases - Capitalized Phrases (CAPs): (learn more)
None Instruction, None Description, Insert Entry, Programming Note, Remove Entry, Common Architecture, Software Note, Mnemonic Operation, Offset Description, Illegal Instruction Machine Checks Description, Three Entries, Privileged Instruction Instruction, Convert Quadword, Illegal Operand Instruction, Litmus Test, Bit Description, Fbv Exceptions, Instruction Summary, Reserved Reserved, Zero Format, Inexact Enable, Integer Overflow Instruction, One Entry, Register Greater Than, Register Less Than New!
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Front Cover | Table of Contents | First Pages | Index | Back Cover | Surprise Me!
Alpha is a 64-bit load/store RISC architecture that is designed with particular emphasis on the three elements that most affect performance: clock speed, multiple instruction issue, and multiple processors. Read the first page Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
longword queue, illegal operand exception, processor issue sequence, translation buffer invalidate, secondary interlock, service routine entry point, logout area, octaword aligned, interlocked resident, memory management fault, primary bootstrap image, underflow enable, asynchronous system traps, invalid operation trap, kernel stack pointer, privileged context block, arithmetic trap, internal processor register, swap privileged context, interlocked insertions, software interrupt level, restart parameter block, system cycle counter, unused function codes, quadword aligned Key Phrases - Capitalized Phrases (CAPs): (learn more)
None Instruction, None Description, Insert Entry, Programming Note, Remove Entry, Common Architecture, Software Note, Mnemonic Operation, Offset Description, Illegal Instruction Machine Checks Description, Three Entries, Privileged Instruction Instruction, Convert Quadword, Illegal Operand Instruction, Litmus Test, Bit Description, Fbv Exceptions, Instruction Summary, Reserved Reserved, Zero Format, Inexact Enable, Integer Overflow Instruction, One Entry, Register Greater Than, Register Less Than New!
Books on Related Topics | Concordance | Text Stats Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Index | Back Cover | Surprise Me!
Citations (learn more)
18
books
cite this book:
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- Itanium Architecture for Programmers: Understanding 64-Bit Processors and EPIC Principles by James S. Evans on page 20, page 410, and Back Matter
- Encyclopedia of Computer Science and Technology (Encyclopedia of Computer Science & Technology Suppl. 23) by Allen Kent on page 273
- Job Scheduling Strategies for Parallel Processing: IPPS '96 Workshop, Honolulu, Hawaii, April 16, 1996. Proceedings (Lecture Notes in Computer Science) by Dror G. Feitelson on page 198
- Field Programmable Logic and Applications: 7th International Workshop, FPL '97, London, UK, September, 1-3, 1997, Proceedings. (Lecture Notes in Computer Science) by Wayne Luk on page 343
- Rdb, Third Edition: A Comprehensive Guide by Lilian Hobbs PhD in Back Matter
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