The Mixed-Signal Boundary-Scan Test Bus is the natural complement to the widely used Boundary-Scan IEEE Std. 1149.1, commonly known as JTAG. This new Mixed-Signal standard is called IEEE Standard 1149.4 and is mainly dedicated to the manufacturing test of analog and mixed-signal boards. But like the IEEE 1149.1 it can be used for many other purposes: the test buses and their digital control form a very general `analog data highway'. Increasingly, mixed-signal boards are gaining complexity, making their testing process extremely challenging. At the same time, IC complexity and technology are getting so sophisticated that testing ICs at the board level becomes very expensive. Embedding a part of the board tester on chip is the aim of the IEEE 1149.4. Analog and Mixed-Signal Boundary-Scan is a comprehensive treatment of the design, application and structure of the IEEE 1149.4. It updates the information on digital Boundary-Scan and addresses chip designers in a dedicated chapter containing guidance to easily build analog circuits including IEEE 1149.4. A basic metrology and a test strategy with the instrumentation needed for it are also described. Analog and Mixed-Signal Boundary-Scan is essential reading for researchers and professionals who need to understand IEEE Standard 1149.4 and its practical implementation in industry.
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Book Description
Editorial Reviews
About the Author
Adam Osseiran is Professor of Electrical Engineering at the Engineering Institute of Geneva, Switzerland and the European Design and Test Specialist at Fluence Technology Inc., Beaverton, Oregon, USA. He is the present Chair of the IEEE 1149.4 Working Group.
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Analog Boundary-scan,
This review is from: Analog and Mixed-Signal Boundary-Scan: A Guide to the IEEE 1149.4 Test Standard (Frontiers in Electronic Testing) (Hardcover)
Very well written....super expensive
Qustion is whether this will be embracd by the industry. As time marches on this technology will most probably enhanced OR adapted and evolved For an intro suggest reading: http://www.home.agilent.com/upload/cmc_upload/All/ept_phillips.pdf
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Inside This Book
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First Sentence:
Figure 1.1 represents an electrical circuit constructed as a printed circuit assembly (PCA) consisting of a substrate carrying a pattern of conductors (the interconnect) on which separately manufactured components are mounted so that the component pins make electrical contact with the interconnect. Read the first page Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
analog test buses, system output pins, analog boundary module, digitizing receiver, first serial value, system input pins, test bus interface circuit, analog buses, analog function pins, core disconnect, differential interconnect, digital boundary modules, test generation software, analog pins, differential pins, interconnect testing, digital pins, digitizer output, interconnect tests, test access port, simple interconnect, serial path, bypass register, driving nodes, test circuitry Key Phrases - Capitalized Phrases (CAPs): (learn more)
International Test Conference, Monte Carlo, New York, Test Symposium, Standards Board, Working Group, Mandatory Bscan New!
Books on Related Topics | Concordance | Text Stats Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Index | Back Cover | Surprise Me!
Figure 1.1 represents an electrical circuit constructed as a printed circuit assembly (PCA) consisting of a substrate carrying a pattern of conductors (the interconnect) on which separately manufactured components are mounted so that the component pins make electrical contact with the interconnect. Read the first page Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
analog test buses, system output pins, analog boundary module, digitizing receiver, first serial value, system input pins, test bus interface circuit, analog buses, analog function pins, core disconnect, differential interconnect, digital boundary modules, test generation software, analog pins, differential pins, interconnect testing, digital pins, digitizer output, interconnect tests, test access port, simple interconnect, serial path, bypass register, driving nodes, test circuitry Key Phrases - Capitalized Phrases (CAPs): (learn more)
International Test Conference, Monte Carlo, New York, Test Symposium, Standards Board, Working Group, Mandatory Bscan New!
Books on Related Topics | Concordance | Text Stats Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Index | Back Cover | Surprise Me!
Citations (learn more)
This book cites 5
books:
- The Boundary-Scan Handbook by Kenneth P. Parker on page 14, and Back Matter
- Reasoning in Boolean Networks: Logic Synthesis and Verification Using Testing Techniques (Frontiers in Electronic Testing) by Wolfgang Kunz in Front Matter
- Testing and Diagnosis Of Analog Circuits and Systems (Electrical Engineering) by Ruey-Wen Liu in Back Matter
- Formal Equivalence Checking and Design Debugging (Frontiers in Electronic Testing) by Shi-Yu Huang in Front Matter
- Multi-Chip Module Test Strategies (Frontiers in Electronic Testing) by Yervant Zorian in Front Matter
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