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Arithmetic Optimization Techniques for Hardware and Software Design [Kindle Edition]

Kastner/Hosangadi/Fallah
4.0 out of 5 stars  See all reviews (1 customer review)

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Book Description

Obtain better system performance, lower energy consumption, and avoid hand-coding arithmetic functions with this concise guide to automated optimization techniques for hardware and software design. High-level compiler optimizations and high-speed architectures for implementing FIR filters are covered, which can improve performance in communications, signal processing, computer graphics, and cryptography. Clearly explained algorithms and illustrative examples throughout make it easy to understand the techniques and write software for their implementation. Background information on the synthesis of arithmetic expressions and computer arithmetic is also included, making the book ideal for newcomers to the subject. This is an invaluable resource for researchers, professionals, and graduate students working in system level design and automation, compilers, and VLSI CAD.

Editorial Reviews

Book Description

Obtain better system performance, lower energy consumption, and avoid hand-coding arithmetic functions with this concise guide to automated optimization techniques for hardware and software design. High-speed architectures for implementing FIR filters are also covered, whilst clearly explained algorithms and illustrative examples make it easy to understand and implement the techniques.

About the Author

Ryan Kastner is an Associate Professor in the Department of Computer Science and Engineering at the University of California, San Diego. He received his Ph.D. in Computer Science from UCLA in 2002 and has since published over 90 technical papers and two books. His current research interests are in embedded system design, particularly the use of reconfigurable computing devices for digital signal processing.

Anup Hosangadi is a R&D Engineer in the Emulation Group at Cadence Design Systems, Inc. He received his Ph.D. in Computer Engineering from the University of California, Santa Barbara, in 2006 and his research interests include high-level synthesis, combinatorial optimization, and computer arithmetic.

Farzan Fallah is currently an Engineer Director at Envis Corporation, Santa Clara. He received his Ph.D. in Electrical Engineering and Computer Science from MIT in 1999, after which he worked as a Project Leader at Fujitsu Labs of America in Sunnyvale until 2008. Farzan has published over 60 papers and has 20 patents granted or pending. He has received a Best Paper Award at the Design Automation Conference in 1998 and a Best Paper Award at the VLSI Design Conference in 2005. He is currently the co-chair of the Low Power Technical Committee of ACM SIGDA and an associate editor of the ACM Transactions on Design Automation of Electronic Systems.

Product Details

  • File Size: 3681 KB
  • Print Length: 200 pages
  • Simultaneous Device Usage: Up to 4 simultaneous devices, per publisher limits
  • Publisher: Cambridge University Press; 1 edition (March 1, 2010)
  • Sold by: Amazon Digital Services, Inc.
  • Language: English
  • ASIN: B004EHZVUO
  • Text-to-Speech: Enabled
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  • Word Wise: Not Enabled
  • Lending: Enabled
  • Amazon Best Sellers Rank: #2,279,112 Paid in Kindle Store (See Top 100 Paid in Kindle Store)
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2 of 2 people found the following review helpful
4.0 out of 5 stars Very good parts, but uneven March 28, 2013
Format:Hardcover|Verified Purchase
Numerical computation underlies a huge number of applications: media and compression, wireless communication, visual pattern recognition, computer graphics - the list vast and growing, and always hungry for more computing power.

Or, as this book proposes, you could get faster answers from the computation fabric you already have, or get the same computation for less hardware or power. Except in the most unusual applications, engineers rarely hand-code their algorithms in a perfectly optimal form. Instead, they write their algorithms in some high-level language, then generate machine code or synthesize hardware using compilers of various sorts, in notation convenient for humans if less than ideal for the computing engine. The authors propose a set of techniques that can be added to existing compilers to improve the efficiency of number-crunching applications.

The first four chapters cover basics, including existing compilation techniques and optimizations, largely to set the context for the new ideas. Their own contributions start to appear in chapter five, where they propose new uses of existing hardware elements for a common operation: adding not just two numbers at a time, but three or more. Instead of adding two at a time, they show hardware approaches to summing the whole set. These techniques increase gate depth in the adder, but nowhere near as much as two-at-a-time addition, and don't take nearly as much time or control logic as multi-cycle operations.

The real contributions appear in later chapters, though. These are where the authors demonstrate novel algorithms for simplifying polynomials in one or more variables - including polynomial expansions of transcendentals.
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