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Built In Test for VLSI: Pseudorandom Techniques
 
 
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Built In Test for VLSI: Pseudorandom Techniques [Hardcover]

Paul H. Bardell (Author), W. H. McAnney (Author), J. Savir (Author)
4.5 out of 5 stars  See all reviews (2 customer reviews)

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Book Description

0471624632 978-0471624639 October 1987 1
This handbook provides ready access to all of the major concepts, techniques, problems, and solutions in the emerging field of pseudorandom pattern testing. Until now, the literature in this area has been widely scattered, and published work, written by professionals in several disciplines, has treated notation and mathematics in ways that vary from source to source. This book opens with a clear description of the shortcomings of conventional testing as applied to complex digital circuits, revewing by comparison the principles of design for testability of more advanced digital technology. Offers in-depth discussions of test sequence generation and response data compression, including pseudorandom sequence generators; the mathematics of shift-register sequences and their potential for built-in testing. Also details random and memory testing and the problems of assessing the efficiency of such tests, and the limitations and practical concerns of built-in testing.

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From the Publisher

This handbook provides ready access to all of the major concepts, techniques, problems, and solutions in the emerging field of pseudorandom pattern testing. Until now, the literature in this area has been widely scattered, and published work, written by professionals in several disciplines, has treated notation and mathematics in ways that vary from source to source. This book opens with a clear description of the shortcomings of conventional testing as applied to complex digital circuits, revewing by comparison the principles of design for testability of more advanced digital technology. Offers in-depth discussions of test sequence generation and response data compression, including pseudorandom sequence generators; the mathematics of shift-register sequences and their potential for built-in testing. Also details random and memory testing and the problems of assessing the efficiency of such tests, and the limitations and practical concerns of built-in testing.

Product Details

  • Hardcover: 368 pages
  • Publisher: Wiley-Interscience; 1 edition (October 1987)
  • Language: English
  • ISBN-10: 0471624632
  • ISBN-13: 978-0471624639
  • Product Dimensions: 9.6 x 6.4 x 0.9 inches
  • Shipping Weight: 1.4 pounds (View shipping rates and policies)
  • Average Customer Review: 4.5 out of 5 stars  See all reviews (2 customer reviews)
  • Amazon Best Sellers Rank: #750,313 in Books (See Top 100 in Books)

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1 of 1 people found the following review helpful:
5.0 out of 5 stars BEST TEST BOOK, October 25, 1995
By A Customer
This review is from: Built In Test for VLSI: Pseudorandom Techniques (Hardcover)
This is the best test book I have read. It covers all aspects of BIST with emphasis on pseudorandom techniques. It does not cover as much about testing as "Digital System Testing and Testable Design" but it is well worth its price tag.
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4.0 out of 5 stars Great Digital test book, March 5, 2009
This review is from: Built In Test for VLSI: Pseudorandom Techniques (Hardcover)
This is a great book written from professionals in the materia. I personally took the class with Dr. Savir and he is not only a great professor but this book is well worth purchasing.

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Inside This Book (learn more)
First Sentence:
Testing of digital circuits is a major portion of the effort in their design, production, and use. Read the first page
Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
possible error polynomials, reconverging gate, boldfaced path, masking probability, path delay test, system data lines, random pattern testable, unequal inversion parities, random pattern testing, test generation effort, controllability values, sampling polynomial, dependency polynomial, cutting algorithm, possible error sequences, reconverging paths, signature dictionary, input signal probabilities, masking probabilities, capture clock, signature analyzer, random pattern testability, scan latches, fault detection probabilities, transition counting
Key Phrases - Capitalized Phrases (CAPs): (learn more)
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