An authoritative book for hardware and software designers. Caches are by far the simplest and most effective mechanism for improving computer performance. This innovative book exposes the characteristics of performance-optimal single and multi-level cache hierarchies by approaching the cache design process through the novel perspective of minimizing execution times. It presents useful data on the relative performance of a wide spectrum of machines and offers empirical and analytical evaluations of the underlying phenomena. This book will help computer professionals appreciate the impact of caches and enable designers to maximize performance given particular implementation constraints.
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A widely read and authoritative book for hardware and software designers. Caches are by far the simplest and most effective mechanism for improving computer performance. This innovative book exposes the characteristics of performance-optimal single and multi-level cache hierarchies by approaching the cache design process through the novel perspective of minimizing execution times. It presents useful data on the relative performance of a wide spectrum of machines and offers empirical and analytical evaluations of the underlying phenomena. This book will help computer professionals appreciate the impact of caches and enable designers to maximize performance given particular implementation constraints. -- Book Description
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An authoritative book for hardware and software designers. Caches are by far the simplest and most effective mechanism for improving computer performance. This innovative book exposes the characteristics of performance-optimal single and multi-level cache hierarchies by approaching the cache design process through the novel perspective of minimizing execution times. It presents useful data on the relative performance of a wide spectrum of machines and offers empirical and analytical evaluations of the underlying phenomena. This book will help computer professionals appreciate the impact of caches and enable designers to maximize performance given particular implementation constraints.
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6 of 6 people found the following review helpful:
3.0 out of 5 stars
Outdated, software-centric,
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This review is from: Cache and Memory Hierarchy Design: A Performance Directed Approach (The Morgan Kaufmann Series in Computer Architecture and Design) (Hardcover)
The big problem with this book is that it's outdated. More than fifteen years old, it studies relatively small kilobyte-sized caches when today's computers are using multi-megabyte caches. The treatment of multi-level caches isn't very strong, and ignores L3 caches completely. The book studies VAX and old RISC architectures, which have some carry-over to today's machines but are not directly applicable. The book doesn't describe MESI or any of the related multi-processor protocols.
The blurb here at Amazon says the book is useful to both software and hardware engineers, though I can't imagine that to be true. The hardware-appropriate details only cover power consumption, and don't deal with partitioning, leveling, associativity imlpementations, concurrency, and so on. But on to the strong points: The book does a great job of explaining how older memory caches work. The main point of the book, in fact, is developing, describing, and studying mathematical models for cache performance and implementation. The author examines a variety of different structures for caches, both in commercial products and in hypothetical architectures. By simulating the performance of the respective machiens, he shows how they really work. Trade-offs between cache size, block size, and set associativity are modeled and graphed very carefully, and the tradeoffs discussed in-depth. I just love some of the sundries the book offers: a thoughtful symbols table explains the variables and the symbols the author consistently uses throughout the book. The biblography is very valuable. though it doesn't cite any papers newer than 1990, it provides a wealth of references for further research. The index could have used a little more attention.
0 of 3 people found the following review helpful:
1.0 out of 5 stars
a book NOT for designer,
This review is from: Cache and Memory Hierarchy Design: A Performance Directed Approach (The Morgan Kaufmann Series in Computer Architecture and Design) (Hardcover)
"If you plane to design a Cache memory system, this book is NOT for you. It's just a collection of statistcal measurements."
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Inside This Book
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First Sentence:
This chapter and the next provide the foundation on which this book rests. Read the first page Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
cycle time penalty, cycle time degradation, global miss ratio, candidate caches, upstream cache, mean memory access time, fetch strategy, compulsory miss rate, fetch strategies, miss ratio ratio, total cycle count, downstream cache, optimal cache size, cache cycle time, cache design space, memory fetch time, fetch size, memory hierarchy design, cache miss cycles, caches greater, main memory access time, set associativity, cache miss penalty, total cache size, optimal block size Key Phrases - Capitalized Phrases (CAPs): (learn more)
Cache Figure, Globally Optimum Cache Design, Cache Parameters Figure, Cycle Count Breakdown, Delayed Read, Main Memory Fetches, Read Miss Time, Relative Main Memory Time Figure New!
Books on Related Topics | Concordance | Text Stats Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Index | Back Cover | Surprise Me!
This chapter and the next provide the foundation on which this book rests. Read the first page Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
cycle time penalty, cycle time degradation, global miss ratio, candidate caches, upstream cache, mean memory access time, fetch strategy, compulsory miss rate, fetch strategies, miss ratio ratio, total cycle count, downstream cache, optimal cache size, cache cycle time, cache design space, memory fetch time, fetch size, memory hierarchy design, cache miss cycles, caches greater, main memory access time, set associativity, cache miss penalty, total cache size, optimal block size Key Phrases - Capitalized Phrases (CAPs): (learn more)
Cache Figure, Globally Optimum Cache Design, Cache Parameters Figure, Cycle Count Breakdown, Delayed Read, Main Memory Fetches, Read Miss Time, Relative Main Memory Time Figure New!
Books on Related Topics | Concordance | Text Stats Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Index | Back Cover | Surprise Me!
Citations (learn more)
This book cites 10
books:
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cites this book:
- Digest of Papers by Compcon in Back Matter (1), Back Matter (2), and Back Matter (3)
- Digest of Technical Papers by IEEE International Pulsed Power Conference in Back Matter (1), Back Matter (2), and Back Matter (3)
- Computer Structures: Readings and Examples (McGraw-Hill computer science series) by C. Gordon Bell in Back Matter
- Probability and Statistics for Modern Engineering by Lawrence L. Lapin in Back Matter
- Principles of Dynamic Programming (Control & Systems Theory Series) (Part I) by Robert Edward Larson in Back Matter
See all 10 books this book cites
- Garbage Collection: Algorithms for Automatic Dynamic Memory Management by Richard Jones in Back Matter
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