This book carefully details design tools and techniques for high-performance ASIC design. Using these techniques, the performance of ASIC designs can be improved by two to three times. Important topics include: Improving performance through microarchitecture; Timing-driven floorplanning; Controlling and exploiting clock skew; High performance latch-based design in an ASIC methodology; Automatically identifying and synthesizing complex logic gates; Automated cell sizing to increase performance and reduce power; Controlling process variation.These techniques are illustrated by designs running two to three times the speed of typical ASICs in the same process generation.
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Editorial Reviews
Review
From the reviews: "This book unveils the mystery behind the performance gap between ASIC and Custom design and shows how to close the gap with minimal design effort. A must read for every ASIC or ASSP designer." (William J. Dally, Professor, Stanford University) "Most IP core providers must provide high-performance designs within the constraints of an ASIC methodology. I'm optimistic that careful application of the techniques in this book will enable me to design embedded processors that do indeed close `the Gap Between ASIC and Custom'." (Kees Vissers, Director of Architecture, Trimedia Technologies Inc.) "This book provides a comprehensive explanation of why ASICs fall so far behind custom ICs in performance, and then shows how better tools, libraries and methodologies can narrow the gap. It's a must read for ASIC designers who want to boost performance - or custom designers who want to speed time to market with ASIC-like design methodologies." (Richard Goering, EDA Editorial Director, EE Times) "I've heard there is a price on the authors' heads. Power Users don't like people who give away their secrets." (Gary Smith, Chief Analyst, Dataquest) "This book reflects the best research to date on understanding the tradeoffs between full-custom intellectual property blocks and synthesized intellectual-property blocks - a topic we could only touch on in the Reuse Methodology Manual. It is required reading for anyone engaged in system-on-a-chip design." (Michael Keating, author of the Reuse Methodology Manual, Vice-President, Synopsys) "Solves one of life's little mysteries[...] It looks like it should become required reading for the IC innovators of this millennium." (Neil Weste, author of Principles of CMOS VLSI Design, Cisco Systems, Inc.)
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4 of 4 people found the following review helpful:
5.0 out of 5 stars
A study of fast processor design,
By Jonah Probell "Jonah Probell" (Silicon Valley & Boston) - See all my reviews
This review is from: Closing the Gap Between ASIC & Custom: Tools and Techniques for High-Performance ASIC Design (Hardcover)
Whether trying to maximize the speed of a standard cell ASIC processor design or minimize the design time of a full custom processor this book describes, in detail, the considerations involved. The authors draw on real-world designs and extensively review several in particular. The book describes the impact on resulting processor performance of pipeline depth, clock tree design, register and latch choice, setup and clock-to-q times, slack passing, dynamic logic, logic design style, richness of standard cell library, wire and transistor sizing, floorplanning and other layout concerns, and the exploitation of process variation.This book focuses strictly on processor circuit design and does not discuss software design, instruction set architecture, or die size and power issues.
5.0 out of 5 stars
Shows the way.,
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This review is from: Closing the Gap Between ASIC & Custom: Tools and Techniques for High-Performance ASIC Design (Hardcover)
This is a very useful book to help focus on how to develop high performance designs. It is a little dated on the technologies covered but gets the job done. One thing to remember is that microprocessor development methods usually will become ASIC development methods after a number of years and related EDA tool development.
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Inside This Book
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First Sentence:
This book begins with a fascinating question: Why are custom circuits so much faster than application-specific integrated circuits (ASICs)? Read the first page Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
unbalanced pipeline stages, slack passing, optimal latch positions, active high latches, transparent high latches, duty cycle jitter, slack bucket, worst case process conditions, active low latches, technology independent metrics, transparent low latches, timing overhead, wire load models, slack graph, combinational delay, combinational logic delay, setup time constraint, register overhead, datapath cells, synthesizable design, unique transistors, generation logic technology, global skew, useful skew, reference clock edge Key Phrases - Capitalized Phrases (CAPs): (learn more)
Proceedings of the International Conference, Journal of Solid-State Circuits, International Solid-State Circuits Conference, Actual Frequency, Design Automation Conference, Base Xtensa, International Electron Devices Meeting, First Encounter, Digest of Technical Papers, University of California, Computer Aided Design, Computer Design, Design Compiler, Predicted Frequency, Tensilica Xtensa, Microprocessor Report, Texas Instruments, High-Performance Microprocessor Design, Intel Pentium, Market Frequency, San Francisco, What's the Problem, Computer Consulting, Massachusetts Institute of Technology, Processors Chart New!
Books on Related Topics | Concordance | Text Stats Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Index | Back Cover | Surprise Me!
This book begins with a fascinating question: Why are custom circuits so much faster than application-specific integrated circuits (ASICs)? Read the first page Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
unbalanced pipeline stages, slack passing, optimal latch positions, active high latches, transparent high latches, duty cycle jitter, slack bucket, worst case process conditions, active low latches, technology independent metrics, transparent low latches, timing overhead, wire load models, slack graph, combinational delay, combinational logic delay, setup time constraint, register overhead, datapath cells, synthesizable design, unique transistors, generation logic technology, global skew, useful skew, reference clock edge Key Phrases - Capitalized Phrases (CAPs): (learn more)
Proceedings of the International Conference, Journal of Solid-State Circuits, International Solid-State Circuits Conference, Actual Frequency, Design Automation Conference, Base Xtensa, International Electron Devices Meeting, First Encounter, Digest of Technical Papers, University of California, Computer Aided Design, Computer Design, Design Compiler, Predicted Frequency, Tensilica Xtensa, Microprocessor Report, Texas Instruments, High-Performance Microprocessor Design, Intel Pentium, Market Frequency, San Francisco, What's the Problem, Computer Consulting, Massachusetts Institute of Technology, Processors Chart New!
Books on Related Topics | Concordance | Text Stats Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Index | Back Cover | Surprise Me!
Citations (learn more)
This book cites 8
books:
See all 8 books this book cites
- Digest of Technical Papers by IEEE International Pulsed Power Conference on 9 pages
- Digital Integrated Circuits (2nd Edition) by Jan M. Rabaey on page 100, page 143, and page 167
- Digital Systems Engineering by William J. Dally on page 141, and page 286
- Computer Architecture: A Quantitative Approach, Second Edition by John L. Hennessy on page 29, and page 55
- Design of High-Performance Microprocessor Circuits by Anantha Chandrakasan on page 208, and page 360
See all 8 books this book cites
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