Explains how to use low power design in an automated design flow, and examine the design time and performance trade-offs Includes the latest tools and techniques for low power design applied in an ASIC design flow Focuses on low power in an automated design methodology, a much neglected area
Closing the Power Gap between ASIC & Custom
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Book Description
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From the Back Cover
This book carefully details design tools and techniques for realizing low power and energy efficiency in a highly productive design methodology. Important topics include: - Microarchitectural techniques to reduce energy per operation - Power reduction with timing slack from pipelining - Analysis of the benefits of using multiple supply and threshold voltages - Placement techniques for multiple supply voltages - Verification for multiple voltage domains - Improved algorithms for gate sizing, and assignment of supply and threshold voltages - Power gating design automation to reduce leakage - Relationships among statistical timing, power analysis, and parametric yield optimization Design examples illustrate that these techniques can improve energy efficiency by two to three times.
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Most Helpful Customer Reviews
1 of 1 people found the following review helpful:
5.0 out of 5 stars
A study of low-power processor design,
By Jonah Probell "Jonah Probell" (Silicon Valley & Boston) - See all my reviews
This review is from: Closing the Power Gap between ASIC & Custom: Tools and Techniques for Low Power Design (Hardcover)
Recently the requirements for my processor design work have shifted from maximizing performance to minimizing power consumption. This new book from the authors of "Closing the Gap between ASIC & Custom" was published at just the right time. It follows a similar format as the previous book, but instead discusses the considerations involved in minimizing power consumption of processors. The authors again draw extensively on real-world chip design examples and have included contributions from a range of industry experts.
This is a book for chip designers and processor architects. It covers the contribution of and techniques to minimize power consumption from the major factors in processors of leakage, active switching, and clock tree. The book does not discuss the design of software or system hardware outside of processor chips such as batteries, displays, or transceivers. As academics, the authors have insight into many leading edge design techniques and many companies' commercial chip designs. I know of no other book on low power design that is as deep or thorough a treatment of the subject as this one.
4.0 out of 5 stars
A good book for those who are counting on low power,
By Italian Job (Sunnny California) - See all my reviews
This review is from: Closing the Power Gap between ASIC & Custom: Tools and Techniques for Low Power Design (Hardcover)
While most of the topics covered in this book should be nothing new to those who are familiar with DFP, the book provides very good examples and analysis of why things should be done in a certain way and where tradeoffs can be made. Even though on the technology side (remember 130nm anybody?) it is a bit out-of-date but the underlying techniques do not change much. From time to time the authors would refer to real life examples to illustrate a point which is a lot more useful than throwing you a ton of equations. For those of you who just want to get the distilled version of the book you can google the same topic and find a similar paper and a presentation (around DAC2003) for free. If you want everything, then this is a very worthwhile book to have in your library.
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Inside This Book
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Key Phrases - Statistically Improbable Phrases (SIPs):
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design compiler, power envelope, media processor, energy efficient design, transistor sizing, gate downsizing, upsizing moves, tcomb total, gate input pin capacitances, largest power saving, minimized netlists, useful clock skew, slew impact, switch cell area, larger power savings, sufficient timing slack, sizing baseline, gates that fan, pipeline imbalance, using multiple supply voltages, power gating, designs using voltage islands, supply voltage assignment, gate sizing, larger gate sizes Key Phrases - Capitalized Phrases (CAPs): (learn more)
Journal of Solid-State Circuits, Design Automation Conference, Computer Aided Design, International Symposium, Computer-Aided Design, International Conference, Power Gating Design Automation, Kluwer Academic Publishers, Uncertain Era, Feng Shui, Winning the Power Struggle, University of California, University of Michigan, Low-Power Electronics Design, Journal of Solid State Circuits, Computer Design, David Chinnery, Custom Integrated Circuits Conference, Berkeley Berkeley, Required Average Time Per Instruction, Netlist Power, Core Duo, Minimizing Power Consumption, System Level Interconnect Prediction Workshop, Configuration Area Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Index | Surprise Me!
design compiler, power envelope, media processor, energy efficient design, transistor sizing, gate downsizing, upsizing moves, tcomb total, gate input pin capacitances, largest power saving, minimized netlists, useful clock skew, slew impact, switch cell area, larger power savings, sufficient timing slack, sizing baseline, gates that fan, pipeline imbalance, using multiple supply voltages, power gating, designs using voltage islands, supply voltage assignment, gate sizing, larger gate sizes Key Phrases - Capitalized Phrases (CAPs): (learn more)
Journal of Solid-State Circuits, Design Automation Conference, Computer Aided Design, International Symposium, Computer-Aided Design, International Conference, Power Gating Design Automation, Kluwer Academic Publishers, Uncertain Era, Feng Shui, Winning the Power Struggle, University of California, University of Michigan, Low-Power Electronics Design, Journal of Solid State Circuits, Computer Design, David Chinnery, Custom Integrated Circuits Conference, Berkeley Berkeley, Required Average Time Per Instruction, Netlist Power, Core Duo, Minimizing Power Consumption, System Level Interconnect Prediction Workshop, Configuration Area Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Index | Surprise Me!
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