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Co-verification of Hardware and Software for ARM SoC Design (Embedded Technology)
 
 

Co-verification of Hardware and Software for ARM SoC Design (Embedded Technology) [Paperback]

Jason Andrews (Author)
5.0 out of 5 stars  See all reviews (1 customer review)

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Book Description

0750677309 978-0750677301 August 30, 2004
Hardware/software co-verification is how to make sure that embedded system software works correctly with the hardware, and that the hardware has been properly designed to run the software successfully -before large sums are spent on prototypes or manufacturing.

This is the first book to apply this verification technique to the rapidly growing field of embedded systems-on-a-chip(SoC). As traditional embedded system design evolves into single-chip design, embedded engineers must be armed with the necessary information to make educated decisions about which tools and methodology to deploy. SoC verification requires a mix of expertise from the disciplines of microprocessor and computer architecture, logic design and simulation, and C and Assembly language embedded software. Until now, the relevant information on how it all fits together has not been available. Andrews, a recognized expert, provides in-depth information about how co-verification really works, how to be successful using it, and pitfalls to avoid. He illustrates these concepts using concrete examples with the ARM core - a technology that has the dominant market share in embedded system product design. The companion CD-ROM contains all source code used in the design examples, a searchable e-book version, and useful design tools.

* The only book on verification for systems-on-a-chip (SoC) on the market

* Will save engineers and their companies time and money by showing them how to speed up the testing process, while still avoiding costly mistakes

* Design examples use the ARM core, the dominant technology in SoC, and all the source code is included on the accompanying CD-Rom, so engineers can easily use it in their own designs

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Frequently Bought Together

Co-verification of Hardware and Software for ARM SoC Design (Embedded Technology) + The Definitive Guide to the ARM Cortex-M3, Second Edition + ARM System Developer's Guide: Designing and Optimizing System Software (The Morgan Kaufmann Series in Computer Architecture and Design)
Price For All Three: $173.94

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Editorial Reviews

Review

"Jason Andrews is one of the acknowledged world's experts in hardware/software verification. His unique knowledge, spanning both hardware design and software development, has enabled him to come up with breakthrough design tools and methodologies solving many of today's most pressing verification challenges. This is one of the most important books to come on the scene in the last ten years." Gary Smith, Chief Analyst, Design & Engineering, Gartner Dataquest

Book Description

Faster time to market, increased confidence in designs, and higher productivity through shorter testing times can be achieved via co-verification- this book shows you how!

Product Details

  • Paperback: 288 pages
  • Publisher: Newnes (August 30, 2004)
  • Language: English
  • ISBN-10: 0750677309
  • ISBN-13: 978-0750677301
  • Product Dimensions: 9.2 x 7.5 x 0.8 inches
  • Shipping Weight: 1.4 pounds (View shipping rates and policies)
  • Average Customer Review: 5.0 out of 5 stars  See all reviews (1 customer review)
  • Amazon Best Sellers Rank: #1,496,557 in Books (See Top 100 in Books)

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Most Helpful Customer Reviews

2 of 4 people found the following review helpful:
5.0 out of 5 stars Co-verification for dummies??, July 24, 2006
By 
Shankar Hemmady "Verification Guru" (Silicon Valley, California, USA) - See all my reviews
(REAL NAME)   
This review is from: Co-verification of Hardware and Software for ARM SoC Design (Embedded Technology) (Paperback)
Jason Andrews' book is one of the nicest, smooth-flowing books I have read recently.

I often avoid reading technical books, since they do not flow at all! Jason has made system verification come out alive and easy for people like me using scores of practical real-life examples. It is very helpful for chip designers and verification engineers/executives like me who are slowly moving up the food chain to system-level for SoC development and design re-use.

What's more -- the book is a lot more reasonably than many others on similar topics! I bought my copy at almost a third of the price I have paid for similar books!

-Shankar@Hemmady.com
Founder, Guru Technologies. Chip verification consultant/manager at Fujitsu, HP, Intel, Xerox, and twelve other companies since the 1990s
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Inside This Book (learn more)
First Sentence:
It works! These are two of the most gratifying words engineers may ever hear. Read the first page
Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
simulation timestamp, soft macrocell, uses separate instruction, simulation acceleration, verilog memory, hardware debugging tools, procedural assertions, logic simulator, software debugger, bus functional model, tightly coupled memory, embedded system software, associative algorithm, hardware design process, hardware modeler, emulation system, instruction set simulation, data breakpoint, endian mode, lint tools, initialization software, instruction set simulator, verification platform, implicit access, logic simulation
Key Phrases - Capitalized Phrases (CAPs): (learn more)
Hardware Design Figure, Mentor Graphics, Cadence Design Systems, Wrapping Address
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