Computer Architecture: A Quantitative Approach, 3rd Edition [Hardcover]

John L. Hennessy (Author), David A. Patterson (Author)

Book Description

ISBN-10: 1558605967 | ISBN-13: 978-1558605961 | Publication Date: May 31, 2002 | Edition: 3

This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today. In this edition, the authors bring their trademark method of quantitative analysis not only to high performance desktop machine design, but also to the design of embedded and server systems. They have illustrated their principles with designs from all three of these domains, including examples from consumer electronics, multimedia and web technologies, and high performance computing.

The book retains its highly rated features: Fallacies and Pitfalls, which share the hard-won lessons of real designers; Historical Perspectives, which provide a deeper look at computer design history; Putting it all Together, which present a design example that illustrates the principles of the chapter; Worked Examples, which challenge the reader to apply the concepts, theories and methods in smaller scale problems; and Cross-Cutting Issues, which show how the ideas covered in one chapter interact with those presented in others. In addition, a new feature, Another View, presents brief design examples in one of the three domains other than the one chosen for Putting It All Together.

The authors present a new organization of the material as well, reducing the overlap with their other text, Computer Organization and Design: A Hardware/Software Approach 2/e, and offering more in-depth treatment of advanced topics in multithreading, instruction level parallelism, VLIW architectures, memory hierarchies, storage devices and network technologies.

Also new to this edition, is the adoption of the MIPS 64 as the instruction set architecture. In addition to several online appendixes, two new appendixes will be printed in the book: one contains a complete review of the basic concepts of pipelining, the other provides solutions a selection of the exercises. Both will be invaluable to the student or professional learning on her own or in the classroom.

Hennessy and Patterson continue to focus on fundamental techniques for designing real machines and for maximizing their cost/performance.

* Presents state-of-the-art design examples including:
* IA-64 architecture and its first implementation, the Itanium
* Pipeline designs for Pentium III and Pentium IV
* The cluster that runs the Google search engine
* EMC storage systems and their performance
* Sony Playstation 2
* Infiniband, a new storage area and system area network
* SunFire 6800 multiprocessor server and its processor the UltraSPARC III
* Trimedia TM32 media processor and the Transmeta Crusoe processor

* Examines quantitative performance analysis in the commercial server market and the embedded market, as well as the traditional desktop market.
Updates all the examples and figures with the most recent benchmarks, such as SPEC 2000.
* Expands coverage of instruction sets to include descriptions of digital signal processors, media processors, and multimedia extensions to desktop processors.
* Analyzes capacity, cost, and performance of disks over two decades.
Surveys the role of clusters in scientific computing and commercial computing.
* Presents a survey, taxonomy, and the benchmarks of errors and failures in computer systems.
* Presents detailed descriptions of the design of storage systems and of clusters.
* Surveys memory hierarchies in modern microprocessors and the key parameters of modern disks.
* Presents a glossary of networking terms.

Editorial Reviews

From the Back Cover

This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today. In this edition, the authors bring their trademark method of quantitative analysis not only to high performance desktop machine design, but also to the design of embedded and server systems. They have illustrated their principles with designs from all three of these domains, including examples from consumer electronics, multimedia and web technologies, and high performance computing.

The book retains its highly rated features: Fallacies and Pitfalls, which share the hard-won lessons of real designers; Historical Perspectives, which provide a deeper look at computer design history; Putting it all Together, which present a design example that illustrates the principles of the chapter; Worked Examples, which challenge the reader to apply the concepts, theories and methods in smaller scale problems; and Cross-Cutting Issues, which show how the ideas covered in one chapter interact with those presented in others. In addition, a new feature, Another View, presents brief design examples in one of the three domains other than the one chosen for Putting It All Together.

The authors present a new organization of the material as well, reducing the overlap with their other text, Computer Organization and Design: A Hardware/Software Approach 2/e, and offering more in-depth treatment of advanced topics in multithreading, instruction level parallelism, VLIW architectures, memory hierarchies, storage devices and network technologies.

Also new to this edition, is the adoption of the MIPS 64 as the instruction set architecture. In addition to several online appendixes, two new appendixes will be printed in the book: one contains a complete review of the basic concepts of pipelining, the other provides solutions a selection of the exercises. Both will be invaluable to the student or professional learning on her own or in the classroom.

Hennessy and Patterson continue to focus on fundamental techniques for designing real machines and for maximizing their cost/performance.

Features

• Presents state-of-the-art design examples including:
  
  • IA-64 architecture and its first implementation, the Itanium
    
  • Pipeline designs for Pentium III and Pentium IV
    
  • The cluster that runs the Google search engine
    
  • EMC storage systems and their performance
    
  • Sony Playstation 2
    
  • Infiniband, a new storage area and system area network
    
  • SunFire 6800 multiprocessor server and its processor the UltraSPARC III
    
  • Trimedia TM32 media processor and the Transmeta Crusoe processor
  
  
  
• Examines quantitative performance analysis in the commercial server market and the embedded market, as well as the traditional desktop market.
  Updates all the examples and figures with the most recent benchmarks, such as SPEC 2000.
  
• Expands coverage of instruction sets to include descriptions of digital signal processors, media processors, and multimedia extensions to desktop processors.
  
• Analyzes capacity, cost, and performance of disks over two decades.
  Surveys the role of clusters in scientific computing and commercial computing.
  
• Presents a survey, taxonomy, and the benchmarks of errors and failures in computer systems.
  
• Presents detailed descriptions of the design of storage systems and of clusters.
  
• Surveys memory hierarchies in modern microprocessors and the key parameters of modern disks.
  
• Presents a glossary of networking terms.

About the Author

John L. Hennessy is the president of Stanford University, where he has been a member of the faculty since 1977 in the departments of electrical engineering and computer science. Hennessy is a fellow of the IEEE and the ACM, a member of the National Academy of Engineering, the National Academy of Science, the American Academy of Arts and Sciences, and the Spanish Royal Academy of Engineering. He received the 2001 Eckert-Mauchly Award for his contributions to RISC technology, the 2001 Seymour Cray Computer Engineering Award, and shared the John von Neumann award in 2000 with David Patterson. After completing the project in 1984, he took a one-year leave from the university to co-found MIPS Computer Systems, which developed one of the first commercial RISC microprocessors. After being acquired by Silicon Graphics in 1991, MIPS Technologies became an independent company in 1998, focusing on microprocessors for the embedded marketplace. As of 2004, over 300 million MIPS microprocessors have been shipped in devices ranging from video games and palmtop computers to laser printers and network switches. Hennessy's more recent research at Stanford focuses on the area of designing and exploiting multiprocessors. He helped lead the design of the DASH multiprocessor architecture, the first distributed shared-memory multiprocessors supporting cache coherency, and the basis for several commercial multiprocessor designs, including the Silicon Graphics Origin multiprocessors. Since becoming president of Stanford, revising and updating this text and the more advanced Computer Architecture: A Quantitative Approach has become a primary form of recreation and relaxation.

David A. Patterson was the first in his family to graduate from college (1969 A.B UCLA), and he enjoyed it so much that he didn't stop until a PhD, (1976 UCLA). After 4 years developing a wafer-scale computer at Hughes Aircraft, he joined U.C. Berkeley in 1977. He spent 1979 at DEC working on the VAX minicomputer. He and colleagues later developed the Reduced Instruction Set Computer (RISC). By joining forces with IBM's 801 and Stanford's MIPS projects, RISC became widespread. In 1984 Sun Microsystems recruited him to start the SPARC architecture. In 1987, Patterson and colleagues wondered if tried building dependable storage systems from the new PC disks. This led to the popular Redundant Array of Inexpensive Disks (RAID). He spent 1989 working on the CM-5 supercomputer. Patterson and colleagues later tried building a supercomputer using standard desktop computers and switches. The resulting Network of Workstations (NOW) project led to cluster technology used by many startups. He is now working on the Recovery Oriented Computing (ROC) project. In the past, he served as Chair of Berkeley's CS Division, Chair and CRA. He is currently serving on the IT advisory committee to the U.S. President and has just been elected President of the ACM. All this resulted in 150 papers, 5 books, and the following honors, some shared with friends: election to the National Academy of Engineering; from the University of California: Outstanding Alumnus Award (UCLA Computer Science Department), McEntyre Award for Excellence in Teaching (Berkeley Computer Science), Distinguished Teaching Award (Berkeley); from ACM: fellow, SIGMOD Test of Time Award, Karlstrom Outstanding Educator Award; from IEEE: fellow, Johnson Information Storage Award, Undergraduate Teaching Award, Mulligan Education Medal, and von Neumann Medal.

Product Details

• Hardcover: 1136 pages
• Publisher: Morgan Kaufmann; 3 edition (May 31, 2002)
• Language: English
• ISBN-10: 1558605967
• ISBN-13: 978-1558605961
• Product Dimensions: 9.5 x 7.8 x 2.2 inches
• Shipping Weight: 4.6 pounds
• Average Customer Review: 3.6 out of 5 stars  See all reviews (22 customer reviews)
• Amazon Best Sellers Rank: #311,015 in Books (See Top 100 in Books)

Customer Reviews

Most Helpful Customer Reviews

28 of 33 people found the following review helpful:

5.0 out of 5 stars The milestone and its third edition, July 29, 2002

By 

G. Avvinti (Sicily, Italy) - See all my reviews
(REAL NAME)   

This review is from: Computer Architecture: A Quantitative Approach, 3rd Edition (Hardcover)

First, this is certainly not an introductory text on Computer Architectures. The authors assume that people reading it have already had an introductory class or some experience. Simply put, the book is not intended to explain how cache memory works, but to present a thourough quantitative analysis to show why and when one implementation works better than another, and what improvements have been devised recently to speed this or this other measurement.
Of course, the best choice for this book would be to have it preceeded by "Computer Organization: the HW/SW interface" (aka CO-HSI), by the same authors, since it would help to better comprehend the MIPS64 and the low-level design behind it, since CO-HSI develop an older version of the MIPS itself.

This is for sure one of the most informative books I've ever encountered both as a student and as a SW engineer. It contains an overwhelming quantity of data, tips, warnings, tecniques so that the over 1100 pages seem incredibly dense. And don't be fooled the book is "only so little": there are other seven online appendixes that can be downloaded, that will add up to more than 250 pages to the book.
As experience teaches, however, quantity does not always mean quality. Yet, it seems this doesn't apply to this book, because the quality of its content is highly informative and interesting for those involved with true CA designs.

Since the first chapter it's clear that target of the book is not a survery of CAs, but a guide through the bunch of considerations and problems a design of a new CA must cope with today. I mean today because much of the data collected and presented is binded to (and updated to) the current edition and its realease date. So covered CAs for this 3ed will feature IA-64 or Sony Playstation II among the others. Nonetheless, it would be misleading to think that next year the book will become useless. Most of the considerations the authors develop and present are quite long lasting (the usage patterns of ISAs, e.g., have incurred little change since the second edition, six years ago).

This edition presents noticeable changes, even if there's no doubt the core is that of CA-AQA 2ed. To mention a few, the first chapter is of course almost totally new since it's the most time-bounded of the book. The elder chapter four (Advanced Pipelining and Instruction Level Parallellism) has been expanded into two chapters, one dealing with Hardware approaches and one with Software approaches (and both with hybrid ones). This goes into great benefit for the reader since it seems we never get enough details on modern CAs and their complexity otherwise.
However, changes has been done even in the way of reductions, and that's especially true for the elder chapter three (Pipelining). It was a full 100 pages chapter, featuring an astonishing treatment of the topic, that has been fundamental in my class of CA II. In the 3ed edition, this chapter has been moved to a shorter appendix at the end, and I think this appendix can't compare with its predecessor (even if some of the "cut" topics have been then spread through chapters 3-4 in the 3ed).

About the exposition of the topics, the authors have built a solid way to make things clear for students and not, beginners and not on quantitative analysis. The book is full of figures, graph, citation and feature a wide bibliography at the end of the book and a reasoned set of references at the end of each chapter.

The only difficulties reading this book will arise only because of the complexity of the topics, who themselves require a fair amount of attention, not because of the language which keeps always clear and straightforward.

This said, I think the book is a fully deserved 5 stars one, with no concurrents on its kind, scope and utility. That's probabily why it has been worlwide used since its first edition.

5 of 5 people found the following review helpful:

4.0 out of 5 stars Great Text, horrible excercises, May 19, 2005

By 

J. Lovell "just a guy" - See all my reviews
(REAL NAME)   

This review is from: Computer Architecture: A Quantitative Approach, 3rd Edition (Hardcover)

This is an excellent text for people with very good reading comprehension. DO NOT TOUCH this book if you skim or often have to read other texts multiple times before you understand what is being said. It's very precisely worded, but also very densely worded. If you are not prepared to pay close attention you will feel lost and abused.

As an example, a prior review roasted this book with this quote: "As they say about the Intel 80x86 architecture: "An architecture with flaws cannot be successful".

The truth is that the text actually lists "An architecture with flaws cannot be successful" as an example of false thinking, and the reviewer simply didn't read closely enough. The 80x86 chips are given AS PROOF that the statement is a fallacy, not as proof of an unsuccessful architecture!

The excercises are even worse, in my opinion. They're far to open ended to assign to a student without further explanation as to what the instructor wants. Also, the text deliberately avoids some topics entirely, on the assumption that the reader will already have the needed familiarity. Not everyone will, so I recommend first reading "Computer Organization and Design: The Hardware/Software Interface" by the same authors. It covers more basics, at the cost of fewer details.

Neither text is for the layman. It is important that you already feel comfortable with basic concepts of electronics (for the hardware) and programming (for the software). If not, start with books designed for the layman.

Despite these flaws, I recommed this book highly. If you approach this book with an attitude of genuine interest, you will learn a great deal about how computers work, and how they have come to work that way.

10 of 13 people found the following review helpful:

5.0 out of 5 stars Comprehensive text, solid examples, July 25, 2002

By 

David Williams "I.T. consultant" (Newcastle, NSW, Australia) - See all my reviews
(REAL NAME)   

This review is from: Computer Architecture: A Quantitative Approach, 3rd Edition (Hardcover)

This hefty tome (883 pages plus appendices) is now in its 3rd edition, and still remains possibly the standard text in its genre.

Seeing this book brought back memories of second-year Computer Science 11 years ago where I learned the comparative virtues of the now-gone VAX computer's massively complex instruction set compared to the sleek RISC SPARC processor and its optimisation opportunities through pipelining a machine instruction's execution stages.

If the above makes no sense to you, or you'd rather not be bogged down with the mathematics of predicting branching when caching, then perhaps this is not the book for you. In fact, it's hard to imagine any casual hobbyist or home user or even the bulk of IT professionals finding much to suit their needs (let alone comprehend!), except in an academic capacity.

Don't get me wrong though - that's not to say this book is valueless, and the truth is far from it. Those who persevere will be rewarded with precise and in-depth technical discussion of modern processor designs - including the Sony PlayStation 2, the cluster that runs the Google search engine, advanced topics in multithreading, instruction-level parallelism, analysis of capacity, costs and performance of disks over two decades and so much more.

Undoubtedly, the book is highly specialised and simply will not appeal to the majority of readers, but with equal certainty it is still surely one of the leading texts in its field, retaining relevance with this updated 3rd edition. If you aspire to become a leading scientist at Intel or AMD then this book is a must.

Oh - and future students beware - chapters still conclude with exercises, but still only a handful actually have solutions presented, hence making all the others possible candidates for assignment questions!