The 2nd edition of defect oriented testing has been extensively updated. New chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering have been added to provide a link between defect sources and yield. The chapter on RAM testing has been updated with focus on parametric and SRAM stability testing. Similarly, newer material has been incorporated in digital fault modeling and analog testing chapters. The strength of Defect Oriented Testing for nano-Metric CMOS VLSIs lies in its industrial relevance.
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
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Book Description
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Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. As the variation of fundamental parameters such as channel length, threshold voltage, thin oxide thickness and interconnect dimensions goes well beyond acceptable limits, new test methodologies and a deeper insight into the physics of defect-fault mappings are needed. In Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits state of the art of defect-oriented testing is presented from both a theoretical approach as well as from a practical point of view. Step-by-step handling of defect modeling, defect-oriented testing, yield modeling and its usage in common economics practices enables deeper understanding of concepts. The progression developed in this book is essential to understand new test methodologies, algorithms and industrial practices. Without the insight into the physics of nano-metric technologies, it would be hard to develop system-level test strategies that yield a high IC fault coverage. Obviously, the work on defect-oriented testing presented in the book is not final, and it is an evolving field with interesting challenges imposed by the ever-changing nature of nano-metric technologies. Test and design practitioners from academia and industry will find that Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits lays the foundations for further pioneering work.
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fault modeling, inductive fault analysis, logic circuits, bridge type, resistive open defects, decoder defects, transistor level fault models, periphery tile, fault model development, equivalent fault classes, gate delay fault model, bitbar lines, average critical area, functional fault coverage, faults using inductive fault analysis, coupling fault, test algorithm development, extracted faults, power supply ramp, resistive defects, analog testing, manufacturing process defects, gate oxide shorts, soft defects, fault simulation results Key Phrases - Capitalized Phrases (CAPs): (learn more)
International Test Conference, Defect-oriented Analog Testing, Journal of Electronic Testing, Journal of Solid State Circuits, Test of Computers, Design Automation Conference, Electron Devices, Computer Aided Design, Kluwer Academic Publishers, Integrated Circuits, International Workshop, Random Access Memories, Wait March, Noise Figure, Pineda de Gyvez, Open Type, Test Symposium, Circuits Figure, Proceedings of European Test Conference, Memory Technology, New York, International Conference, Circuits Table, Metal Diff, Carnegie Mellon University New!
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Front Cover | Table of Contents | First Pages | Index | Surprise Me!
fault modeling, inductive fault analysis, logic circuits, bridge type, resistive open defects, decoder defects, transistor level fault models, periphery tile, fault model development, equivalent fault classes, gate delay fault model, bitbar lines, average critical area, functional fault coverage, faults using inductive fault analysis, coupling fault, test algorithm development, extracted faults, power supply ramp, resistive defects, analog testing, manufacturing process defects, gate oxide shorts, soft defects, fault simulation results Key Phrases - Capitalized Phrases (CAPs): (learn more)
International Test Conference, Defect-oriented Analog Testing, Journal of Electronic Testing, Journal of Solid State Circuits, Test of Computers, Design Automation Conference, Electron Devices, Computer Aided Design, Kluwer Academic Publishers, Integrated Circuits, International Workshop, Random Access Memories, Wait March, Noise Figure, Pineda de Gyvez, Open Type, Test Symposium, Circuits Figure, Proceedings of European Test Conference, Memory Technology, New York, International Conference, Circuits Table, Metal Diff, Carnegie Mellon University New!
Concordance | Text Stats Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Index | Surprise Me!
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