In 2007 The Design, Automation and Test in Europe (DATE) conference celebrated its tenth anniversary. As a tribute to the chip and system-level design and design technology community, this book presents a compilation of the three most influential papers of each year. This provides an excellent historical overview of the evolution of a domain that contributed substantially to the growth and competitiveness of the circuit electronics and systems industry.
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From the Back Cover
The Design, Automation and Test in Europe (DATE) conference celebrated in 2007 its tenth anniversary. As a tribute to the chip and system-level design and design technology community, this book presents a compilation of the three most influential papers of each year. This provides an excellent historical overview of the evolution of a domain that contributed substantially to the growth and competitiveness of the circuit electronics and systems industry. The papers were grouped in six sections: System Level Design; Networks on Chip; Modeling, Simulation and Run-Time Management; Digital Systems in CMOS and Beyond; Physical Design and Validation; and Test and Verification. The winners of the prestigious EDAA Lifetime Achievement Award as well as other recognized experts in their field wrote an introduction to each section, summarizing the history in their domain and indicating how the selected DATE papers contributed to it.
About the Author
Dr. Rudy Lauwereins is the General Chair for DATE 2007, Dr. Jan Madsen is the Technical Chair.
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abstract data model, system level design, speedup factor, step response, double window, extreme value theory, ramp response, output latch, stream context information, encoded bus lines, avalanche diode array fabricated, optimal voltage schedule, interconnect tuning, unate form, source synchronous links, dedicated hardware fifos, routing path allocation, network synthesis methodology, semantic unit composition, event stream contexts, glitch width, target fault list, coding transistors, communication delay estimates, test response evaluator Key Phrases - Capitalized Phrases (CAPs): (learn more)
Europe-The Most Influential, Monte Carlo, Design Automation Conference, Statistical Blockade, Computer-Aided Design, International Conference, Multiobjective Core-Based Single-Chip System Synthesis, Test Symposium, International Test Conference, Han Carlson, Improving Compression Ratio, Software Codesign, Far End Line, Kluwer Academic, Temporary Faults-Detecting Technique, Single Photon Avalanche Diode Array Fabricated, Computer Design, Performance-Aware Mapping, New York, Quantitative Comparison of Power Management Algorithms, Compositional Specification of Behavioral Semantics, Efficient Inductance Extraction, Technical Report, Finite State Machine, Savings Trans Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Surprise Me!
abstract data model, system level design, speedup factor, step response, double window, extreme value theory, ramp response, output latch, stream context information, encoded bus lines, avalanche diode array fabricated, optimal voltage schedule, interconnect tuning, unate form, source synchronous links, dedicated hardware fifos, routing path allocation, network synthesis methodology, semantic unit composition, event stream contexts, glitch width, target fault list, coding transistors, communication delay estimates, test response evaluator Key Phrases - Capitalized Phrases (CAPs): (learn more)
Europe-The Most Influential, Monte Carlo, Design Automation Conference, Statistical Blockade, Computer-Aided Design, International Conference, Multiobjective Core-Based Single-Chip System Synthesis, Test Symposium, International Test Conference, Han Carlson, Improving Compression Ratio, Software Codesign, Far End Line, Kluwer Academic, Temporary Faults-Detecting Technique, Single Photon Avalanche Diode Array Fabricated, Computer Design, Performance-Aware Mapping, New York, Quantitative Comparison of Power Management Algorithms, Compositional Specification of Behavioral Semantics, Efficient Inductance Extraction, Technical Report, Finite State Machine, Savings Trans Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Surprise Me!
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