This book is the second of two volumes addressing the design challenges associated with new generations of semiconductor technology. The various chapters are compiled from tutorials presented at workshops in recent years by prominent authors from all over the world. Technology, productivity and quality are the main aspects under consideration to establish the major requirements for the design and test of upcoming systems on a chip.
Design of Systems on a Chip: Design and Test
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About the Author
Ricardo Reis is a former president of the Brazilian Computer Society and former vice-president of the Brazilian Microelectronics Society. He is now trustee of both societies. He is a trustee and former vice-president of the International Federation for Information Processing, IFIP. He received the Silver Core Award from IFIP. He is member of IFIP TC10 and WG 10.5. He is the Editor-in-Chief of the Journal of Integrated Circuits and Systems, JICS. Ricardo is also Member of the Editorial Board Latin America liaison of the IEEE D&T as Latin America liaison. He contributed to the organizing and program committees of several a large number of international conferences (like VLSI-SoC, ISVLSI, ISSS+CODES, PATMOS, RAW, LATW, SBCCI, IFIP World Congress, …) and he is a founder of the SBCCI conference series (Symposium on Integrated Circuits and Systems Design). He is also Editor of several books.
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Inside This Book
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core internal test, mask gate arrays, serial transistors, core creator, behavioral synthesis, physical design automation, surrounding logic, average wire length, concurrent error detection, fault modelling, boundary scan cells, high fault coverage, communication synthesis, testable design, fault simulation, legal schedule, data flow graph, architecture generation, bare dies, scan chains, peripheral access, buf size, detailed routing, microelectronic systems, packed words Key Phrases - Capitalized Phrases (CAPs): (learn more)
Design Automation Conference, International Conference, European Design, Design of Systems, International Test Conference, Test of Computers, Kluwer Academic Publishers, International Symposium, Test Symposium, New York, Constraint Analysis, The Netherlands, Computer Society, Porto Alegre, Boolean Oracle, Micro Analysis System, Ben Ismail, Computer Design, Journal of Electronic Testing, Los Alamitos, Microprocessor Report, Midwest Symposium, Rio Grande, Technical Report, User Defined Logic New!
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Front Cover | Table of Contents | First Pages | Index | Surprise Me!
core internal test, mask gate arrays, serial transistors, core creator, behavioral synthesis, physical design automation, surrounding logic, average wire length, concurrent error detection, fault modelling, boundary scan cells, high fault coverage, communication synthesis, testable design, fault simulation, legal schedule, data flow graph, architecture generation, bare dies, scan chains, peripheral access, buf size, detailed routing, microelectronic systems, packed words Key Phrases - Capitalized Phrases (CAPs): (learn more)
Design Automation Conference, International Conference, European Design, Design of Systems, International Test Conference, Test of Computers, Kluwer Academic Publishers, International Symposium, Test Symposium, New York, Constraint Analysis, The Netherlands, Computer Society, Porto Alegre, Boolean Oracle, Micro Analysis System, Ben Ismail, Computer Design, Journal of Electronic Testing, Los Alamitos, Microprocessor Report, Midwest Symposium, Rio Grande, Technical Report, User Defined Logic New!
Concordance | Text Stats Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Index | Surprise Me!
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