A recent technological advance is the art of designing circuits to test themselves, referred to as a Built-In Self-Test. This book is written from a designer's perspective and describes the major BIST approaches that have been proposed and implemented, along with their advantages and limitations.
A Designer's Guide to Built-in Self-Test
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4.0 out of 5 stars
good coverage of BIST methods,
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This review is from: A Designer's Guide to Built-in Self-Test (Frontiers in Electronic Testing) (Hardcover)
Built-in Self-Test is now highly desirable in chip design. As the linewidth keeps decreasing, and the number of transistors rises, the sheer complexity necessitates BIST as a basic design principle. Hence Stroud offers you a recent and timely survey of BIST methods. The writing quality is not bad, and he gives a good coverage of the most common methods used in the industry.
Whether some of these prove practical in your situation is another matter, of course. If you have existing standard cells that you must use, or conform to, and a fab with specific design rules, then some BIST methods might be precluded.
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Inside This Book
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First Sentence:
There are three phases in the life-cycle of a product where testing is of critical importance. Read the first page Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
output response compaction, general sequential logic, loopback multiplexers, register adjacency, fault simulation time, bridging fault coverage, combinational logic cone, loopback data, multiple capture cycles, undefined logic value, data path circuitry, product term lines, dominant bridging fault model, normal system mode, dominant bridging faults, logic cones, analog output response, pattern sensitivity faults, single precision accumulator, path sensitization algorithm, physical layout generator, scan design techniques, test point insertion, actual fault coverage, intended system function Key Phrases - Capitalized Phrases (CAPs): (learn more)
Designer's Guide, Designers Guide, Autonomous Test, Built-In Self Test, Count Value Holding Register, Cellular Automata, Bell Labs, Pattern Control, Shift Control, System Circuit, Magnitude Register, Cyclic Redundancy Check, Done Controller, Programmable Shift Register, Area Overhead Performance Approach Flip-Flops, Continuous Time State Variable Filter, Differential Pair, Elliptical Filter, Leapfrog Filter, Low Pass Filter, N-bit Accum Reg, Single Stage Common-Emitter Amp, Start Controller, Write Read New!
Books on Related Topics | Concordance | Text Stats Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Index | Back Cover | Surprise Me!
There are three phases in the life-cycle of a product where testing is of critical importance. Read the first page Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
output response compaction, general sequential logic, loopback multiplexers, register adjacency, fault simulation time, bridging fault coverage, combinational logic cone, loopback data, multiple capture cycles, undefined logic value, data path circuitry, product term lines, dominant bridging fault model, normal system mode, dominant bridging faults, logic cones, analog output response, pattern sensitivity faults, single precision accumulator, path sensitization algorithm, physical layout generator, scan design techniques, test point insertion, actual fault coverage, intended system function Key Phrases - Capitalized Phrases (CAPs): (learn more)
Designer's Guide, Designers Guide, Autonomous Test, Built-In Self Test, Count Value Holding Register, Cellular Automata, Bell Labs, Pattern Control, Shift Control, System Circuit, Magnitude Register, Cyclic Redundancy Check, Done Controller, Programmable Shift Register, Area Overhead Performance Approach Flip-Flops, Continuous Time State Variable Filter, Differential Pair, Elliptical Filter, Leapfrog Filter, Low Pass Filter, N-bit Accum Reg, Single Stage Common-Emitter Amp, Start Controller, Write Read New!
Books on Related Topics | Concordance | Text Stats Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Index | Back Cover | Surprise Me!
Citations (learn more)
This book cites 23
books:
See all 23 books this book cites
- Computer Engineering by C.Gordon Bell in Front Matter (1), and Front Matter (2)
- Murray Hill by Chales Mercer in Front Matter
- Fault Tolerant and Fault Testable Hardware Design by Parag K. Lala in Back Matter
- Boundary-Scan Interconnect Diagnosis (Frontiers in Electronic Testing) by José T. de Sousa in Front Matter
- Multi-Chip Module Test Strategies (Frontiers in Electronic Testing) by Yervant Zorian in Front Matter
See all 23 books this book cites
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