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Designing with FPGAs and CPLDs
 
 
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Designing with FPGAs and CPLDs [Paperback]

Bob Zeidman (Author)
4.0 out of 5 stars  See all reviews (7 customer reviews)

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Book Description

1578201128 978-1578201129 September 2002 1
* Choose the right programmable logic devices and development tools * Understand the design, verification, and testing issues * Plan schedules and allocate resources efficiently Choose the right programmable logic devices with this guide to the technolog

Designing with FPGAs and CPLDs guides readers through choosing the right programmable logic devices, understanding the design, verification, and testing issues involved with them, and more.

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Editorial Reviews

About the Author

Bob Zeidman is the president of The Chalkboard Network, an e-learning company for high-tech professionals. He is also president of Zeidman Consulting, a hardware and software contract development firm. Since 1983, he has designed CPLDs, FPGAs, ASI


Product Details

  • Paperback: 220 pages
  • Publisher: CMP; 1 edition (September 2002)
  • Language: English
  • ISBN-10: 1578201128
  • ISBN-13: 978-1578201129
  • Product Dimensions: 9.2 x 7.4 x 0.7 inches
  • Shipping Weight: 1.1 pounds (View shipping rates and policies)
  • Average Customer Review: 4.0 out of 5 stars  See all reviews (7 customer reviews)
  • Amazon Best Sellers Rank: #1,718,581 in Books (See Top 100 in Books)

More About the Author

Bob is the president and founder of Software Analysis and Forensic Engineering Corporation (www.SAFE-corp.biz), the leading provider of software intellectual property analysis tools. Bob is considered a pioneer in the field of analyzing software intellectual property, having created the CodeSuite(R) program for detecting software IP theft and measuring software IP growth.

Bob Zeidman is also the president and founder of Zeidman Consulting (www.ZeidmanConsulting.com), a premier contract research and development firm in Silicon Valley that now focuses on consulting to law firms about intellectual property disputes. Since 1983, Bob has designed computer chips and circuit boards for RISC-based parallel processor systems, laser printers, network switches and routers, and other complex systems. His clients have included Apple Computer, Cisco Systems, Cadence Design Systems, Facebook, Intel, and Texas Instruments, and Zynga. Bob has worked on and testified in cases involving billions of dollars in disputed intellectual property.

Bob is a prolific writer and instructor, giving seminars at conferences around the world. Among his publications are numerous articles on engineering and business as well as fourt textbooks -- The Software IP Detective's Handbook, Designing with FPGAs and CPLDs, Verilog Designer's Library, and Introduction to Verilog. Bob holds multiple patents and earned two bachelor's degrees, in physics and electrical engineering, from Cornell University and a master's degree in electrical engineering from Stanford University.

Bob is active in a number of nonprofits, sitting on the boards of several. He also enjoys writing novels and screenplays and has won a number of awards for these works of fiction.

 

Customer Reviews

7 Reviews
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Most Helpful Customer Reviews

12 of 12 people found the following review helpful:
4.0 out of 5 stars Lightweight but good overview, July 4, 2004
By 
Simon Glass "rare reader" (Christchurch New Zealand) - See all my reviews
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This review is from: Designing with FPGAs and CPLDs (Paperback)
I bought this book to get started on FPGA design.

I found the book to be an mixture of high level concepts (how to test designs, design methodology) and low level (converting async. logic to sync.). With my little knowledge of Verilog this was fairly useful.

I can't help feeling that the book is aimed at engineering managers rather than engineers.

I liked the explanation of the internal structure of various PLDs. This gives a reasonable understanding of how these devices work, which is always a good thing. I also liked the design/test guidelines in Chapter 5. This gives a good overview of pitfalls and a basis for attacking a design, albeit quite briefly.

I didn't like the brevity and the 'overview' nature of much of the material. The book needs a big brother to actually get into the topics properly - I believe the Author has written a good book on Verilog so maybe that helps. I found the chapter on tools very dissappointing - it left me with a vague understanding of the various tools, but I would have liked a summary of available tools and information on costs and performance.

Taking out the questions and a few over-long code samples, the book has only around 150 pages of actual material, in fairly large print. It took 2-3 hours to read carefully.

Overall this book is a strange animal, but I found it fairly useful.

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15 of 16 people found the following review helpful:
1.0 out of 5 stars Very Simple: 12 years too late, June 17, 2003
By 
Austin Lesea (Los Gatos, Ca United States) - See all my reviews
This review is from: Designing with FPGAs and CPLDs (Paperback)
Although well written, readable, and accurate in the information presented, the book is 12 years out of date. The preface implies that the book will help the reader choose the "right" FPGA or CPLD, but only deals with the most generic criteria.

A better title would be "Introduction to FPGAs and CPLDs for Managers".

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10 of 11 people found the following review helpful:
5.0 out of 5 stars Very well written. Exactly what I was looking for., March 2, 2004
By 
Darrell F Thayer (Quakertown, PA USA) - See all my reviews
This review is from: Designing with FPGAs and CPLDs (Paperback)
I am an experienced embedded software engineer and part time digital design engineer. I was looking for a CPLD/FPGA book to help me with my first CPLD design. This was for a circuit that delivered highly accurate aircraft altitude to an autopilot system (very important stuff). I needed the following from a CPLD/FPGA book:
- An overview of CPLD/FPGA technology.
- How CPLDs and FPGAs have changed the way we must perform digital design (from the old days).
- Practical rules for creating proper synchronous design.

As the author (Bob Zeidman) points out, different sections of the book are intended for different audiences. For me, chapters 1 (history), 2 (CPLDS), and 5 (Design Techniques, Rules, and Guidelines) were the most important. I do not yet use FPGAs nor HDLs (though VHDL is in my near future). I never expect any book to answer all my questions; however, this one clearly answered the important questions I needed answered.

I used Altera's "MAX+PLUS II" tools to create, simulate (test) and program my circuit. Great tools, never crashed, excellent online help system and tutorials.

This book was critical in helping me design a reliable, testable, accurate circuit using synchronous design techniques. The circuit flies today in many business commuter aircraft.

By the way, there are some minor errors in the book (do you know of any books without errors?). I emailed Bob about it (the book gives you his URL and email address). Bob not only sent me errata information in like 2 hours, but provided an additional in depth explanation for an issue I was having with state machine design. Bob is also posting the errata info on his website - not THAT is customer service!

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Inside This Book (learn more)
First Sentence:
Programmable devices have progressed through a long evolution to reach the complexity today to support an entire system on a chip (SOC). Read the first page
Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
floating buses, equivalency checking, clock input pins, route software, synchronous design, level design description, redundant logic, hold time violation, power consumption numbers, toggle coverage, input clk, behavioral blocks, combinatorial logic, posedge clk, static timing analysis, end endmodule, programmable elements, timing simulation, programmable devices, configurable logic blocks, programmable interconnect, gate level design, bus contention, floating nodes, synthesis software
Key Phrases - Capitalized Phrases (CAPs): (learn more)
Universal Design Methodology, Altera Corporation, Silicon Valley, Xilinx Inc, The Masked Gate Array
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