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Digital Phase Lock Loops: Architectures and Applications [Hardcover]

Saleh R. Al-Araji (Author), Zahir M. Hussain (Author), Mahmoud A. Al-Qutayri (Author)

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Book Description

October 19, 2006 0387328637 978-0387328638 1
This exciting new book covers various types of digital phase lock loops. It presents a comprehensive coverage of a new class of digital phase lock loops called the time delay tanlock loop (TDTL). It also details a number of architectures that improve the performance of the TDTL through adaptive techniques that overcome the conflicting requirements of the locking rage and speed of acquisition.

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About the Author

Prof. Al-Araji received the B.Sc., M.Sc., and Ph.D. degrees from the University of Wales Swansea, (UK), all in electrical engineering in 1968, 1969, and 1972 respectively. Since September 2002, Professor Al-Araji was appointed Professor and Head of Communications Engineering Department at Etisalat University College (Emirates Telecommunication Cooperation), Sharjah, UAE. Prior to that and for six years he was working at the Transmission Network Systems, Scientific-Atlanta, Atlanta, Georgia, USA as Senior Staff Electrical Engineer. During the academic year 1995/1996, Prof. Al-Araji was visiting professor at the Ohio State University, Columbus, Ohio, USA. He was visiting professor at King’s College, University of London, England, during the summers of 1988 and 1989. Prof. Al-Araji was professor and Department Head at the University of Baghdad, Iraq, and the University of Yarmouk, Jordan. Prof. Al-Araji was awarded the British IERE Clerk Maxwell Premium for a paper published in 1976 and the Scientific-Atlanta award for outstanding achievement in the year 2000. He was an Iraqi National member of URSI Commissions C and D, and the ITU (CCIR Group 8). His research interests include synchronization techniques, communication signal processing, and CATV systems and networks. He has published over 50 papers in international Journals and Conferences and holds 6 US Patents and one International Patent. He is a reviewer to a number of international conferences and journals, and is involved in the organization of a number of international conferences in various capacities. Prof. Al-Araji is a senior member of the IEEE. His e-mail address is: alarajis@euc.ac.ae.

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Inside This Book (learn more)
Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
architectures for improved performance, phase error detector, same frequency step, initial phase error, locking boundary, digital controlled oscillator, independent locking, locking range, steady state phase error, phase estimator, phase pdf, phase random variable, principal interval, kth sampling instant, lock range, locking performance, free running frequency, time delay unit, fixed point analysis, digital phase locked loop, first order loop, second order loop, locking conditions, phase plane plot, loop filter
Key Phrases - Capitalized Phrases (CAPs): (learn more)
System Generator, Xilinx Blockset, Time Figure, Filter Detector, Sic Cell
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