Customer Reviews

Digital Systems Design with VHDL and Synthesis: An Integrated Approach

5 star:		(6)
4 star:		(2)
3 star:		(1)
2 star:		(1)
1 star:		(1)

 

 

The book organization is unique in that the codes are all complete from beginning to end with line numbers. The author explains the relevant codes line by line. However, as the book progresses, he explains less details of the codes. Another unique feature (the best feature) is that every code comes with synthesized circuits along with synthesis commands of how to optimize for different goals (i.e. best timing or best area). The practical examples are real life examples (i.e. microprocessor, FIFO, FIR filter, DRAM etc.) The reader will also get design fundamentals of the above examples. Overall, an excellent book!

When first starting VHDL, I picked up this book and found it somewhat hard to follow. After some initial reading, I had to give up and put it on the shelf, and then began looking for other easy books to read. One after another, I finally bought a dozen of VHDL books, some of which I wished I had not. Among these books, I found that Andrew Rushton's "VHDL for Logic Synthesis 2nd" is a wonderful beginner's reading; I got some VHDL coding skills with "Essential VHDL, RTL Syntheses Done Right" by Sundar Rajan; Peter Ashenden's "Designer's Guide to VHDL" is good, but too thick to read from cover to cover; Kevin Skahill taught me important programmable logic concept with "VHDL for Programmable Logic"...

After all these books, I still felt uncertain, lack of something. Then I came to understand that I needed some good real world design examples, something real, not just demo. I took this book again from the shelf, Woo, totally different now! This was what I needed now. The author doesn't waste time telling me which is better, Verilog or VHDL, or which is the more useful package, std_logic_arith or numeric_std. He just shows me with excellent examples what real world engineers do in their projects; so I gradually understand what I will do in face with real world problems. By now I learnt to know that when possible I'll use std_logic_arith package in my design in spite of its proprietary, because by doing so one can get rid of worrying about type conversions at the ports, and therefore avoid possible mistakes in the code; I know how to use logic hiding, source sharing, variable using skills to get better designs.

The author provides more examples in his new book: "Digital Systems Design With Vhdl and Synthesis: An Integrated Approach", but after reading them over and again, I still think the first book is better. In my opinion, it's really concise and to the point. Though there are some minor problems with it, such as incomplete references, lack of important package listings, I give it solid five stars!

This book is not for beginners. It seems great as a reference, with clear examples and good discussion on each line of the examples. Along with the associated synthesized logic diagrams, it helps make the examples clear. The minuses are that he jumps right into an example, with no help as to how to write VHDL files, setup, or other help. You must know already how to write basic VHDL. Also, as with most books that have great content, the index is very poor.

I agree with previous author that this book is not for beginner and the intention of this book is not for beginner. I will recommend that a beginner read other VHDL books and get familiar with VHDL then read "VHDL - Coding and Logic Synthesis with Synopsys" by Weng Fook Lee and then this book if you want to go into logic synthesis.

The weakness of this book is that it is a little verbose and some of the sentences are not clear. Also the typesetting is not as good as other books, but considering all those great content (and thick too) along with a cheap price, it is an excellent book!

KC Chang did it again! I have Mr. Chang's 1st edition of this text, and I have found it to be an excellent reference material for VHDL design. I read through the text, and I have discovered that his method of explination is both CLEAR and CONCISE. In other words, it is to the point. The codes are explained step-by-step and relevant topics are given further explination...this is extremely helpful for those designing with VHDL. It is a wise investment for my technical career in high speed digital design.

The text from Kevin Skahill is another text that complements this one. Bhaskers is another good complement also. Choose any of the three...THEY ARE ALL GOOD.

I thought this book was completely lacking in what should have been it's primary focus: teaching the constructs and methodology of coding in VHDL, specifically for synthesizable hardware descriptions. The only thing the author did succeed in doing regularly was regurgitating VHDL syntax and standard packages while including pages and pages of code that was extremely poorly explained.

I had already learned Verilog so I am comfortable with what an HDL looks like and I could basically follow what Chang was trying to convey in his code, but not once did I feel that he adequately explain the mechanics or reasoning behind any of his code. The entire book used poor English, and clearly was not proof-read thoroughly by a competent editor. Here is an example passage picked at random:

"The latch enable signal LATCH_EN is generated as follows. A signal FRAMEn_DELAY is generated by delaying FRAMEn by one clock cycle using an inferred D-type flipflop, as shown in lines 22 to 29. LATCH_EN is obtained in line 30."

That's wonderful. This "explanation" is completely useless. It says nothing that isn't already apparent from the code listing. No further explanation is given as to what LATCH_EN is doing, why it's needed, etc. This example is par for the course. Furthermore, NOT A SINGLE COMMENT EXISTS IN ANY CODE LISTING, except when comment syntax is explained or as just a section separator.

I found this book completely inadequate for learning VHDL as a first HDL. If I hadn't already known Verilog, I would have to buy another book to get any insight into anything other than syntax and standard packages, but the use of English was so shaky and distracting that I wouldn't even recommend the book for that purpose. Almost anything would be better than this. Try "A VHDL Primer" or "A VHDL Synthesis Primer" from Bhasker. He wrote clear and concise Verilog books (of the same titles) and I'm sure he would not disappoint.

K.C. Chang's treatment of VHDL synthesis is good and it helps you get a grasp on what some of the tools will generate from your VHDL.

VHDL designers come in a couple of flavors, there are those who know how they want to do something and need to express it in VHDL, and there are those who know what they want something to do and need to know how to tell VHDL to synthesize that. This book caters a bit more to the first group, people who have in their head the circuit they want to synthesize.

In general, I recommend this book as a companion to Ashendon's book (The Designers Guide to VHDL) as that book treats the language more thouroughly. This book does jump right in and assume you've read Chang's other book on VHDL (but the again, the Ashendon book is better in that regard.)

I agree with previous author that this book is not for beginner and the intention of this book is not for beginner. I will recommend that a beginner read other VHDL books and get familiar with VHDL then read "VHDL - Coding and Logic Synthesis with Synopsys" by Weng Fook Lee and then this book if you want to go into logic synthesis.

The weakness of this book is that it is a little verbose and some of the sentences are not clear. Also the typesetting is not as good as other books, but considering all those great content (and thick too) along with a cheap price, it is an excellent book!

This book works through several interesting engineering examples. It isn't a book for learning VHDL, and it is sketchy on details about VHDL syntax. Also the 2 1/8 page Index is very short.

I think the concise review tells it al