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Digital Circuit Testing and Testability (The Morgan Kaufmann Series in Computer Architecture and Design)
 
 
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Digital Circuit Testing and Testability (The Morgan Kaufmann Series in Computer Architecture and Design) [Hardcover]

Parag K. Lala (Author)


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Book Description

0124343309 978-0124343306 January 28, 1997 1
In the past few years, reliable hardware system design has become increasingly important in the computer industry. Digital Circuit Testing and Testability is an easy to use introduction to the practices and techniques in this field.
Parag K. Lala writes in a user-friendly and tutorial style, making the book easy to read, even for the newcomer to fault-tolerant system design. Each informative chapter is self-contained, with little or no previous knowledge of a topic assumed. Extensive references follow each chapter, making further research in a particular area readily available. Each chapter covers a different aspect or technological component of fault-tolerant system design, and this book is an excellent compilation of up-to-date information in an area where such a book is needed.

Key Features
* Contains the most up-to-date information on fault modeling in CMOS devices
* Provides comprehensive coverage of self-checking logic design at the gate and the transistor level
* Discusses the latest techniques available for testing state machines
* Presents a collection of methods for testable logic synthesis
* Provides state-of-the-art information on Built-in-self-testing
* Includes detailed coverage of memory testing
* Discusses all major techniques for fault-tolerant hardware design

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About the Author

The author is currently a Professor in the Department of Electrical Engineering at North Carolina A&T State University. He is the author of more than 75 papers, and three books published by Prentice Hall. His research interests include design for testability, self-checking logic design, automatic logic synthesis of low power logic circuits, andCPLD/FPGA based system design. He received a M.S. from King's College, London, and a Ph.D. from the City University of London.


Product Details

  • Hardcover: 199 pages
  • Publisher: Academic Press; 1 edition (January 28, 1997)
  • Language: English
  • ISBN-10: 0124343309
  • ISBN-13: 978-0124343306
  • Product Dimensions: 9.3 x 6.3 x 0.8 inches
  • Shipping Weight: 1.3 pounds
  • Amazon Best Sellers Rank: #3,158,742 in Books (See Top 100 in Books)

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Inside This Book (learn more)
First Sentence:
A failure is said to have occurred in a circuit or system if it deviates from its specified behavior [1.1]. Read the first page
Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
double cube divisor, verification test set, testable combinational circuits, reachability indices, multiple backtrace, pattern resistant faults, tests for combinational circuits, singular cover, homing sequence, functional fault models, cube divisors, test set derived, logic design structure, distinguishing sequence, boundary scan cells, scan clock, differentiating sequence, coupling fault, bridging faults, signature generator, faulty gate, test generation process, addressable latch, test generation techniques, path delay faults
Key Phrases - Capitalized Phrases (CAPs): (learn more)
Test Conf, Design Automation Conf, Fault-Tolerant Computing, Test Generation Based
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