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ESL Design and Verification: A Prescription for Electronic System Level Methodology (Systems on Silicon)
 
 

ESL Design and Verification: A Prescription for Electronic System Level Methodology (Systems on Silicon) [Hardcover]

Grant Martin (Author), Brian Bailey (Author), Andrew Piziali (Author)
5.0 out of 5 stars  See all reviews (1 customer review)

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Book Description

March 9, 2007 0123735513 978-0123735515 1
Visit the authors' companion site! http://www.electronicsystemlevel.com/ - Includes interactive forum with the authors!

Electronic System Level (ESL) design has mainstreamed - it is now an established approach at most of the world's leading system-on-chip (SoC) design companies and is being used increasingly in system design. From its genesis as an algorithm modeling methodology with 'no links to implementation', ESL is evolving into a set of complementary methodologies that enable embedded system design, verification and debug through to the hardware and software implementation of custom SoC, system-on-FPGA, system-on-board, and entire multi-board systems.

This book arises from experience the authors have gained from years of work as industry practitioners in the Electronic System Level design area; they have seen "SLD" or "ESL" go through many stages and false starts, and have observed that the shift in design methodologies to ESL is finally occurring. This is partly because of ESL technologies themselves are stabilizing on a useful set of languages being standardized (SystemC is the most notable), and use models are being identified that are beginning to get real adoption.

ESL DESIGN & VERIFICATION offers a true prescriptive guide to ESL that reviews its past and outlines the best practices of today.

Table of Contents
CHAPTER 1: WHAT IS ESL?
CHAPTER 2: TAXONOMY AND DEFINITIONS FOR THE ELECTRONIC SYSTEM LEVEL
CHAPTER 3: EVOLUTION OF ESL DEVELOPMENT
CHAPTER 4: WHAT ARE THE ENABLERS OF ESL?
CHAPTER 5: ESL FLOW
CHAPTER 6: SPECIFICATIONS AND MODELING
CHAPTER 7: PRE-PARTITIONING ANALYSIS
CHAPTER 8: PARTITIONING
CHAPTER 9: POST-PARTITIONING ANALYSIS AND DEBUG
CHAPTER 10: POST-PARTITIONING VERIFICATION
CHAPTER 11: HARDWARE IMPLEMENTATION
CHAPTER 12: SOFTWARE IMPLEMENTATION
CHAPTER 13: USE OF ESL FOR IMPLEMENTATION VERIFICATION
CHAPTER 14: RESEARCH, EMERGING AND FUTURE PROSPECTS
APPENDIX: LIST OF ACRONYMS

* Provides broad, comprehensive coverage not available in any other such book
* Massive global appeal with an internationally recognised author team
* Crammed full of state of the art content from notable industry experts

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Product Details

  • Hardcover: 488 pages
  • Publisher: Morgan Kaufmann; 1 edition (March 9, 2007)
  • Language: English
  • ISBN-10: 0123735513
  • ISBN-13: 978-0123735515
  • Product Dimensions: 9.5 x 7.6 x 1.2 inches
  • Shipping Weight: 2.6 pounds (View shipping rates and policies)
  • Average Customer Review: 5.0 out of 5 stars  See all reviews (1 customer review)
  • Amazon Best Sellers Rank: #1,993,753 in Books (See Top 100 in Books)

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3 of 4 people found the following review helpful:
5.0 out of 5 stars Essential for anybody doing Electronic System Level Design, July 18, 2007
By 
David C. Black (Austin, TX United States) - See all my reviews
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This review is from: ESL Design and Verification: A Prescription for Electronic System Level Methodology (Systems on Silicon) (Hardcover)
[NOTE: This is NOT English as a Second Language, despite the advertisers found here. Too many acronyms in the world.]

This is a very good overview of methodologies and approaches for doing ESL design. I heartily recommend this to help plan projects. Read it before you start the project. It should be read by project managers, architects and managers. Engineers should read this and use it to backup their requests for raising the bar in design.

When you're done reading this book and want to go deeper and learn SystemC, consider SystemC: From the Ground Up.
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Inside This Book (learn more)
Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
functional coverage models, time domain accuracy, hardware design flow, extensible processors, assertion coverage, bug diagnosis, electronic system level, verification environment, reference simulator, behavioral compiler, box verification, negative verification, behavioral synthesis tools, coverage closure, design space exploration, transaction level modeling, verification planning, bug discovery, num blocks, implementation artifacts, system design team, err max, silicon industry, verification progress, hardware team
Key Phrases - Capitalized Phrases (CAPs): (learn more)
Accessed November, New York, Accessed October, San Francisco, Mentor Graphics, System Studio, Texas Instruments, Kluwer Academic Publishers, The Netherlands, International Conference, Design Test, Gary Smith, Green Hills Software, University of California, Elsevier-Morgan Kaufmann, Englewood Cliffs, Fixed Dynamic Configurability, Free Software Foundation, Hewlett Packard, Severity One, Big Three, Boca Raton, Discrete Cosine Transform, International Business Strategies, New Orleans
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