The general understanding of design is that it should lead to a manufacturable product. Neither the design nor the process of manufacturing is perfect. As a result, the product will be faulty, will require testing and fixing. Where does economics enter this scenario? Consider the cost of testing and fixing the product. If a manufactured product is grossly faulty, or too many of the products are faulty, the cost of testing and fixing will be high. Suppose we do not like that. We then ask what is the cause of the faulty product. There must be something wrong in the manufacturing process. We trace this cause and fix it. Suppose we fix all possible causes and have no defective products. We would have eliminated the need for testing. Unfortunately, things are not so perfect. There is a cost involved with finding and eliminating the causes of faults. We thus have two costs: the cost of testing and fixing (we will call it cost-1), and the cost of finding and eliminating causes of faults (call it cost-2). Both costs, in some way, are included in the overall cost of the product. If we try to eliminate cost-1, cost-2 goes up, and vice versa. An economic system of production will minimize the overall cost of the product. Economics of Electronic Design, Manufacture and Test is a collection of research contributions derived from the Second Workshop on Economics of Design, Manufacture and Test, written for inclusion in this book.
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Inside This Book
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First Sentence:
Engineers are often concerned with optimizing the technological efficiency. Read the first page Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
partial scan approaches, test strategy planning, expected test length, test strategy planner, detectability clusters, test pattern sequences, using cluster mean, fault spectrum, specified fault coverage, fuzzy optimization models, implementing boundary scan, made scannable, multichip systems, surface mount modules, area array bonding, using boundary scan, tester resources, error detection efficiency, boundary scan cells, scan clock, cost advisor, boundary scan chain, format die, response verification, scan path Key Phrases - Capitalized Phrases (CAPs): (learn more)
Monte Carlo, New York, Kluwer Academic Publishers, Brunel University, The Netherlands, Test of Computers, Test Conf, Multichip Systems Design Advisor, High Value Electronics Division, International Conference, University of Texas, Ellis Horwood, Fault Coverage Fig, Mid-Point Estimate, Pessimistic Estimate, Previous Form, University of Southern California, High Level Test Economics Advisor, Next Form, Node Node Type Test Method, Observed Value, Test Stage Data, The Economics of Automatic Testing, Chartered Engineer, International Workshops New!
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Front Cover | First Pages | Index | Back Cover | Surprise Me!
Engineers are often concerned with optimizing the technological efficiency. Read the first page Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
partial scan approaches, test strategy planning, expected test length, test strategy planner, detectability clusters, test pattern sequences, using cluster mean, fault spectrum, specified fault coverage, fuzzy optimization models, implementing boundary scan, made scannable, multichip systems, surface mount modules, area array bonding, using boundary scan, tester resources, error detection efficiency, boundary scan cells, scan clock, cost advisor, boundary scan chain, format die, response verification, scan path Key Phrases - Capitalized Phrases (CAPs): (learn more)
Monte Carlo, New York, Kluwer Academic Publishers, Brunel University, The Netherlands, Test of Computers, Test Conf, Multichip Systems Design Advisor, High Value Electronics Division, International Conference, University of Texas, Ellis Horwood, Fault Coverage Fig, Mid-Point Estimate, Pessimistic Estimate, Previous Form, University of Southern California, High Level Test Economics Advisor, Next Form, Node Node Type Test Method, Observed Value, Test Stage Data, The Economics of Automatic Testing, Chartered Engineer, International Workshops New!
Books on Related Topics | Concordance | Text Stats Browse Sample Pages:
Front Cover | First Pages | Index | Back Cover | Surprise Me!
Citations (learn more)
This book cites 17
books:
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10
books
cite this book:
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- Economics of Automatic Testing by Brendan Davis on 4 pages
- Economics of Design and Test for Electronic Circuits and Systems (Ellis Horwood Workshops) by Tex.) International Workshop on the Economics of Design and Test (1st : 1991 : Austin on page 66, and page 80
- Systems Design by Isim University on page 80, and page 92
- Conceptual Design of Multichip Modules and Systems (The Springer International Series in Engineering and Computer Science) by Peter A. Sandborn on page 80, and page 92
- Managing Software Development and Maintenance by Carma L. McClure on page 146
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- Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits (Frontiers in Electronic Testing Volume 17) by M. Bushnell in Back Matter (1), Back Matter (2), and Back Matter (3)
- Defect Oriented Testing for CMOS Analog and Digital Circuits (Frontiers in Electronic Testing) by Manoj Sachdev in Front Matter, and page 12
- Research Perspectives and Case Studies in Systems Test and Diagnosis (Frontiers in Electronic Testing) by John W. Sheppard in Front Matter
- Introduction to IDDQ Testing (Frontiers in Electronic Testing) by S. Chakravarty in Front Matter
- Testing and Testable Design of High-Density Random-Access Memories (Frontiers in Electronic Testing) by Pinaki Mazumder in Front Matter
See all 10 books citing this book
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