Customer Reviews

Electronic Design Automation for Integrated Circuits Handbook - 2 Volume Set (Industrial Information Technology)

5 star:		(2)
4 star:		(1)
3 star:		(0)
2 star:		(0)
1 star:		(0)

 

 

I suppose that anyone even thinking about this book realizes that without ways to automate the design today's ever more sophisticated and ever larger chips simply wouldn't exist. There would be no way to manually keep track of the billions of connections required. There would be no laptops, cell phones, digital cameras or any of the other neat little electronic gadgets that we have today.

As is often the case with books that are describing the current state of the art, this book is a collaboration written by a wide range of people in the industry. These people come from a wide variety of organizations including academic, equipment suppliers, semiconductor companies and more. They are located all across the world. The editors are of course from California (where else?).

Volume One covers architecture, design, verification and testing. Volume Two covers RTL to GDS-II, analog and mixed-signal design, physical verification, and technology CAD.

These books represent the state of the art as it existed in 2005 and Early 2006. These are the techniques in use today and are the base for future developments.

Great overview of the IC design process from start to finish. It's been a while since I was a grunt in the trenches working on chip designs - the two volumes allowed me to see what's state of the art all in one place.

This is one of the best coverage on EDA topics I have come across. For people without an EDA background, this book gives a very good understanding of the complexities of the technologies and clearly illustrates the various challenges involved in designing EDA applications.

There are two things that would help supplement the excellent coverage:

1. the "Overview" section could be expanded (maybe as a "Epilogue" section) to cover "key algorithms, key innovations required and potential challenges for future".

2. An example of a reasonably generic "chip" with a mock run of some tool flows as well as the cycle times (to be fair to all EDA vendors, it would have to cover atleast a few popular flows). The focus for this section would be to help EDA users, future software designers and the IT architecture/infrastructure designers to better leverage the information in future optimization efforts.