This book contains papers first presented at the Second International Workshop on Field-Programmable Logic and Applications (FPL '92), held in Vienna, Austria, in August-September 1992. The growing importance of field-programmable devices, especially of field-programmable gate arrays, is demonstrated by the increased number of papers submitted in 1992. Of the 70 papers submitted, 23 were selected for this book. The first three papers were invited and discuss strategic issues and give surveys. Three papers deal with new FPGA architectures and five papers introduce methods and tools. The last twelve papers report applications focusing on rapid prototyping or new FPGA-based computer architectures. The invited papers are: "Overview of complex array-based PLDs" by G. Biehl; "Technologies and utilization of field programmable gate arrays" by J. Isoaho, A. Nummela, and H. Tenhunen; and "Some considerations on field-programmable gate arrays and their impact on system design" by A. Sangiovanni-Vincentelli.
Field-Programmable Gate Arrays
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heuristic tree searching, basic test patterns, expander terms, column adders, deterministic test patterns, isochronic forks, redesigned circuit, test pattern set, using logic synthesis, purpose coprocessor, instruction fetch unit, hardware expense, delay box, logic capacity, hardware effort, configurable logic blocks, execute unit, routing structure, asynchronous circuits, machine paradigm, benchmark circuits, routing delay, placement algorithm, logic cells, programmable gate arrays Key Phrases - Capitalized Phrases (CAPs): (learn more)
University of Technology, International Conference, Technical Report, Department of Computer Science, Xilinx Inc, Wait Queue, Design Automation Conference, Terminate Box, Electronic Design, Erik Brunvand, San Jose, Bell Laboratories, Computer Aided Prototyping, Computer-Aided Design, International Symposium, International Test Conference, New York, Ready Queue Box, University of Strathclyde, Computer Design, Computer Science Press, Flip Flops, Germany Abstract, University of Erlangen, University of Kaiserslautern New!
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heuristic tree searching, basic test patterns, expander terms, column adders, deterministic test patterns, isochronic forks, redesigned circuit, test pattern set, using logic synthesis, purpose coprocessor, instruction fetch unit, hardware expense, delay box, logic capacity, hardware effort, configurable logic blocks, execute unit, routing structure, asynchronous circuits, machine paradigm, benchmark circuits, routing delay, placement algorithm, logic cells, programmable gate arrays Key Phrases - Capitalized Phrases (CAPs): (learn more)
University of Technology, International Conference, Technical Report, Department of Computer Science, Xilinx Inc, Wait Queue, Design Automation Conference, Terminate Box, Electronic Design, Erik Brunvand, San Jose, Bell Laboratories, Computer Aided Prototyping, Computer-Aided Design, International Symposium, International Test Conference, New York, Ready Queue Box, University of Strathclyde, Computer Design, Computer Science Press, Flip Flops, Germany Abstract, University of Erlangen, University of Kaiserslautern New!
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- Advances in Artificial Intelligence 14th Biennial Conference of the Canadian Society for Computational Studies of Intelligence, AI 2001, Ottawa, Canada, June 7-9, 2001: Proceedings by Eleni Stroulia in Back Matter
- Digital Communication by S. Venkata Ram on page 106
- The Logical Processing of Digital Signals (Computer systems engineering series) by Stanley L. Hurst on page 83
- Sequential Logic Synthesis (The Springer International Series in Engineering and Computer Science) by Ashar Djaloeis on page 77
- Logic Programming (Lecture Notes in Artificial Intelligence) by A. Voronkov in Back Matter
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