This volume constitutes the proceedings of the Fifth International Workshop on Field-Programmable Logic and Its Applications, FPL '95, held in Oxford, UK in August/September 1995. The volume presents 46 full revised papers carefully selected by the program committee from a large number and wide range of submissions. The papers document the progress achieved since the predecessor conference (see LNCS 849). They are organized in sections on architectures, platforms, tools, arithmetic and signal processing, embedded systems and other applications, and reconfigurable design and models.
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First Sentence:
In late 1992 Oxford Parallel set out to develop a classification scheme for FPGA3 architectures, with the ultimate aim of identifying the most appropriate architectures for use with the hardware synthesis tools previously developed in the Oxford University Computing Laboratory [1]. Read the first page Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
data parallel code, fault recovery rate, global clock constraint, register file slices, realizable cones, shaft encoder interface, reconfigurable supercomputers, pattern matching circuits, tutorial stack, xnf file, current stack level, code adaption, logic coprocessors, custom computing platform, host transputer, hardware macros, programmable logic data book, tester board, reconfigurable machines, exercise stack, reconfigurable logic, custom computing machines, fault detection test, emulation board, hardware object Key Phrases - Capitalized Phrases (CAPs): (learn more)
San Jose, Computer Society Press, Reference Manual, Xilinx Inc, Virtual Computer, University of Calgary, Viewlogic Systems, Oxford University Computing Laboratory, Computer Science, National Semiconductor, New York, While True, Kluwer Academic Publishers, Laboratory of Electrical Measurement Engineering, Prentice Hall, User's Guide, Communicating Sequential Processes, Computer Aided Prototyping, Configurable Logic Processor, Hardware Promela, John Wiley, Oxford Parallel, Parks Road, University of the Federal Armed Forces, Addison-Wesley Publishing Company New!
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Front Cover | Table of Contents | First Pages | Index | Back Cover | Surprise Me!
In late 1992 Oxford Parallel set out to develop a classification scheme for FPGA3 architectures, with the ultimate aim of identifying the most appropriate architectures for use with the hardware synthesis tools previously developed in the Oxford University Computing Laboratory [1]. Read the first page Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
data parallel code, fault recovery rate, global clock constraint, register file slices, realizable cones, shaft encoder interface, reconfigurable supercomputers, pattern matching circuits, tutorial stack, xnf file, current stack level, code adaption, logic coprocessors, custom computing platform, host transputer, hardware macros, programmable logic data book, tester board, reconfigurable machines, exercise stack, reconfigurable logic, custom computing machines, fault detection test, emulation board, hardware object Key Phrases - Capitalized Phrases (CAPs): (learn more)
San Jose, Computer Society Press, Reference Manual, Xilinx Inc, Virtual Computer, University of Calgary, Viewlogic Systems, Oxford University Computing Laboratory, Computer Science, National Semiconductor, New York, While True, Kluwer Academic Publishers, Laboratory of Electrical Measurement Engineering, Prentice Hall, User's Guide, Communicating Sequential Processes, Computer Aided Prototyping, Configurable Logic Processor, Hardware Promela, John Wiley, Oxford Parallel, Parks Road, University of the Federal Armed Forces, Addison-Wesley Publishing Company New!
Books on Related Topics | Concordance | Text Stats Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Index | Back Cover | Surprise Me!
Citations (learn more)
This book cites 44
books:
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- Computer Arithmetic: Principles, Architecture and Design by Kai Hwang on 4 pages
- Programmable Logic by Intel Corporation on page 20, page 85, and page 138
- Field-Programmable Gate Arrays (The Springer International Series in Engineering and Computer Science) by Stephen D. Brown on page 14, page 67, and page 388
- Computer Arithmetic (Ieee Computer Society Press Tutorial) by Earl E. Swartzlander on page 187, and page 260
- Communicating Sequential Processes (Prentice Hall International Series in Computing Science) by C.A.R. Hoare on page 117, and page 379
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