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Field-Programmable Gate Arrays (The Springer International Series in Engineering and Computer Science)
 
 
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Field-Programmable Gate Arrays (The Springer International Series in Engineering and Computer Science) [Hardcover]

Stephen D. Brown (Author), Robert J. Francis (Author), Jonathan Rose (Author), Zvonko G. Vranesic (Author)


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Book Description

June 30, 1992 0792392485 978-0792392484 1
Field-Programmable Gate Arrays (FPGAs) have emerged as an attractive means of implementing logic circuits, providing instant manufacturing turnaround and negligible prototype costs. They hold the promise of replacing much of the VLSI market now held by mask-programmed gate arrays. FPGAs offer an affordable solution for customized VLSI, over a wide variety of applications, and have also opened up new possibilities in designing reconfigurable digital systems. Field-Programmable Gate Arrays discusses the most important aspects of FPGAs in a textbook manner. It provides the reader with a focused view of the key issues, using a consistent notation and style of presentation. It provides detailed descriptions of commercially available FPGAs and an in-depth treatment of the FPGA architecture and CAD issues that are the subjects of current research. The material presented is of interest to a variety of readers, including those who are not familiar with FPGA technology, but wish to be introduced to it, as well as those who already have an understanding of FPGAs, but who are interested in learning about the research directions that are of current interest.

Product Details

  • Hardcover: 228 pages
  • Publisher: Springer; 1 edition (June 30, 1992)
  • Language: English
  • ISBN-10: 0792392485
  • ISBN-13: 978-0792392484
  • Product Dimensions: 9.6 x 6.4 x 0.8 inches
  • Shipping Weight: 15.8 ounces
  • Amazon Best Sellers Rank: #3,674,414 in Books (See Top 100 in Books)

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Inside This Book (learn more)
Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
logic cells, logic block pin, logic block area, possible input orderings, logic block architecture, logic block functionality, maximum channel density, other wire segments, reconvergent paths, area per block, logic block levels, detailed routing algorithm, percent routing, technology mapper, programmable inversion, wiring segments, horizontal routing channels, block flexibility, coarse graph, detailed router, replication optimization, vertical routing channels, assignment tree, combinational delay, global router
Key Phrases - Capitalized Phrases (CAPs): (learn more)
Field-Programmable Gate Arrays, Commercially Available, Long Lines, General Purpose, Concurrent Logic, Routing Area Per Block, Block Delay, Advanced Micro Devices, Crosspoint Solutions, Single-length Lines
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