Hdl Chip Design: A Practical Guide for Designing, Synthesizing & Simulating Asics & Fpgas Using Vhdl or Verilog [Hardcover]

Douglas J. Smith (Author)

Editorial Reviews

Review

Arthur C. Clarke once wrote that any sufficiently advanced civilization would possess seemingly magical powers to a lesser-advanced one. Technology, and in particular computer technology, has and always will present a Janus head to the world. While delivering enormous capability and freedom, the instrumentality by which that freedom is delivered becomes even more arcane and obscurantist to the users of that technology. The backyard auto mechanic is an artifact. We are all, including most mechanics, relegated to simply filling the gas tank, changing the oil or replacing the occasional black box. And what of those practitioners of these arcane arts, who in designing and building the devices which channel electrons to the exacting demands of industry and consumers seem to take on almost a mantle of priesthood? Any priesthood needs a catechism, and Douglas J. Smith's HDL Chip Design might well fit that role. This publication is designed as an introduction to and reference on using the two industry standard hardware description languages (HDL's) VDHL and Verilog to design, simulate and synthesize Applications-Specific Integrated Circuits (ASIC) and Field Programmable Gate-Arrays (FPGA). Emphasis for modeling is at the RT (register transfer) level, using a top-down design method. This reviewer approached this text as a student with a physics background and an interest in glimpsing the inner sanctum of chip design and came away impressed with its clarity, depth, and no-nonsense approach. This is not a book for the fainthearted neophyte, but a challenging and rewarding introduction to HDL chip design, and a treasury as a reference book to the practicing professional. -- From Independent Publisher

Product Details

• Hardcover: 448 pages
• Publisher: Doone Pubns (March 1998)
• Language: English
• ISBN-10: 0965193438
• ISBN-13: 978-0965193436
• Product Dimensions: 11.3 x 8.6 x 1.4 inches
• Shipping Weight: 3.2 pounds
• Average Customer Review: 3.9 out of 5 stars  See all reviews (21 customer reviews)
• Amazon Best Sellers Rank: #381,231 in Books (See Top 100 in Books)

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Most Helpful Customer Reviews

13 of 14 people found the following review helpful:

5.0 out of 5 stars why you should buy this book, December 5, 1999

By 

Ken Shiring (Raleigh, NC) - See all my reviews

This review is from: Hdl Chip Design: A Practical Guide for Designing, Synthesizing & Simulating Asics & Fpgas Using Vhdl or Verilog (Hardcover)

I am a designer who has worked heavily in both VHDL and Verilog. I have read the other VHDL/Verilog books by Ashenden, Armstrong, Perry, Skahill, and Palnitkar, and this is the definitely the best. It shows by example major concepts you can't get from acedemic texts.

The most important thing about this book is the way it shows you how the synthesis tool interprets your code, which is the single most important aspect of VHDL/Verilog coding. It saves you the frustration of finding out by trial and error, and shows you ways of avoiding nasty synthesis problems.

This book is a must for any serious designer's library, and great for starters as well.

12 of 13 people found the following review helpful:

3.0 out of 5 stars Good Book But be Cautions of Errors, September 6, 2000

By 

Shumin Zhang (Germantown, MD USA) - See all my reviews
(REAL NAME)   

This review is from: Hdl Chip Design: A Practical Guide for Designing, Synthesizing & Simulating Asics & Fpgas Using Vhdl or Verilog (Hardcover)

It is a good book for reference because it has VHDL and Verilog code side by side. It is really helpful if you know one language and want to carry on with another HDL language. The synthesis result listed for each circuit is also helpful for understand what the circuit really up to. But there are some errors in the book, like mis-use of blocking and none-blocking assignment. Do not take the example code as correct for granted. You can try it out in any simulator and see how many error you can catch. Overall, it is good reference, just do not take the examples too seriously.

12 of 13 people found the following review helpful:

2.0 out of 5 stars More of a Cook Book than a Learning Tool, August 28, 1998

By A Customer

This review is from: Hdl Chip Design: A Practical Guide for Designing, Synthesizing & Simulating Asics & Fpgas Using Vhdl or Verilog (Hardcover)

You get this book when you buy Veribest software and since we teach several hundred students with Veribest tools we looked seriously at this book. In the end we rejected it. Its good points are there are lots of examples and it uniquely teaches both VHDL and Verilog concurrently (although we only intend to teach one). Its weak points are really that it teaches nothing other than how to write fragments of VHDL code. No understanding is given of how and why synthesis tools work, what the effect is on complexity or performance of different coding styles nor of overall design methodologies for constructing systems (as opposed to sub components) also there is no future look into developments or issues in synthesis and IC/FPGA design. So we didn't feel that using this book gave our students any long term knowledge or deep understanding of the subject. If all you want to do is write VHDL/Verilog fragments, the book is OK. Otherwise it demonstrates too much and educates too little.