Written by the world’s most prominent microprocessor design leaders from industry and academia, this book provides complete coverage of all aspects of complex microprocessor design: technology, power management, clocking, high-performance architecture, design methodologies, memory and I/O design, computer aided design, testing and design for testability. The chapters provide state-of-the-art knowledge while including sufficient tutorial material to bring non-experts up to speed. A useful companion to design engineers working in related areas.
High-Performance Energy-Efficient Microprocessor Design
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Inside This Book
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Key Phrases - Statistically Improbable Phrases (SIPs):
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fixed output load, intermiss distance, clocked storage elements, fixed input size, optimal total power, leading zero anticipation, mixed size placement, local bit lines, pulsed latch, ling adder, semiconductor scaling, percolation distance, spatial cache, adder core, trailing edge effect, adder topology, clocking strategy, miss facility, temporal cache, parasitic delay, clock uncertainty, clock distribution system, effective subtraction, miss facilities, latching edge Key Phrases - Capitalized Phrases (CAPs): (learn more)
Solid-State Circuits, San Francisco, Design Automation Conf, Moore's Law, Microprocessor Rep, Computer Aided Design, Rent's Rule, Computer Design, Vdd Vdd, John Wiley, Springer Printed, University of California, Clk Figure, Emma Figure, Electronic Computers, Fault Tolerant Computing, Intel Corporation, Kluwer Academic Publishers, New York, One Table, Prentice Hall, Rent Limit, San Jose, Sign Ext, Special Inst New!
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Front Cover | Table of Contents | First Pages | Index | Back Cover | Surprise Me!
fixed output load, intermiss distance, clocked storage elements, fixed input size, optimal total power, leading zero anticipation, mixed size placement, local bit lines, pulsed latch, ling adder, semiconductor scaling, percolation distance, spatial cache, adder core, trailing edge effect, adder topology, clocking strategy, miss facility, temporal cache, parasitic delay, clock uncertainty, clock distribution system, effective subtraction, miss facilities, latching edge Key Phrases - Capitalized Phrases (CAPs): (learn more)
Solid-State Circuits, San Francisco, Design Automation Conf, Moore's Law, Microprocessor Rep, Computer Aided Design, Rent's Rule, Computer Design, Vdd Vdd, John Wiley, Springer Printed, University of California, Clk Figure, Emma Figure, Electronic Computers, Fault Tolerant Computing, Intel Corporation, Kluwer Academic Publishers, New York, One Table, Prentice Hall, Rent Limit, San Jose, Sign Ext, Special Inst New!
Books on Related Topics | Concordance | Text Stats Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Index | Back Cover | Surprise Me!
Citations (learn more)
This book cites 10
books:
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- Microprocessor Design by Vojin Oklobdzija in Front Matter, and page 57
- High Speed Digital Design: A Handbook of Black Magic by Howard Johnson on page 309
- High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices by Stephen H. Hall on page 309
- Digital Integrated Circuits (2nd Edition) by Jan M. Rabaey on page 119
- Reasoning About Parallel Architectures by William W. Collier on page 286
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