Provides coverage of IDDQ testing, including discussion of the correlation between physical defects and logical faults, and how IDDQ testing detects these defects. This title presents information on test generation for IDDQ testing; use of stuck-at and random vectors for IDDQ testing; use of IDDQ testing in factory production lines; cost benefit analysis; instrumentation issues; off-chip and on-chip current senors; ATE interface; case studies with memories and microprocessors; and proposed IEE QTAG standards. It also supplies planning guidelines and optimization methods, together with numerous examples ranging from simple circuits to extensive case studies. It should be useful as a reference for designers and test engineers.
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1 of 1 people found the following review helpful:
3.0 out of 5 stars
Quickly Written - No Meat,
By A Customer
This review is from: Iddq Testing for CMOS VLSI (Hardcover)
This book discusses a few issues involved in IDDQ testing, theauthors research in bridging faults and some research done by Hawkins and Soden.Very little detail is given about On-Chip Current Sensors or the QTAG standard. Other topics like estimating Quiescent Current and fault modeling are only discussed briefly. This book was written as an attempt to get a book out quickly on a "hot" topic. Someone should write an in-depth book discussing all of the pressing IDDQ issues in detail without this "get to market" time constraint. The book however can introduce a novice reader to IDDQ but it is not for an intermediate or advanced engineer. If it was the intent of the author to write a book for novices he should have discussed more basic VLSI Design.
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