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Intel Xeon Phi Coprocessor High-Performance Programming Paperback – March 1, 2013

ISBN-13: 978-0124104143 ISBN-10: 0124104142 Edition: 1st

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Intel Xeon Phi Coprocessor High-Performance Programming + Intel® Xeon Phi™ Coprocessor Architecture and Tools: The Guide for Application Developers (Expert's Voice in Microprocessors) + Structured Parallel Programming: Patterns for Efficient Computation
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Product Details

  • Paperback: 432 pages
  • Publisher: Morgan Kaufmann; 1 edition (March 1, 2013)
  • Language: English
  • ISBN-10: 0124104142
  • ISBN-13: 978-0124104143
  • Product Dimensions: 7.5 x 0.9 x 9.2 inches
  • Shipping Weight: 1.6 pounds (View shipping rates and policies)
  • Average Customer Review: 3.8 out of 5 stars  See all reviews (4 customer reviews)
  • Amazon Best Sellers Rank: #277,926 in Books (See Top 100 in Books)

Editorial Reviews

Review

"Read this book. Authors Jim Jeffers and James Reinders spent two years helping educate customers about the prototype and pre-production hardware before Intel introduced the first Intel Xeon Phi coprocessor. They have distilled their own experiences coupled with insights from many expert customers, to create this authoritative first book on the essentials of programming for this new architecture and these new products."--Slashdot.org, May 5, 2013 "The authors.are uniquely experienced in software development for this new silicon. As a result, this book is the definitive programming reference for the 60+ core monster from Intel.highly readable and interlaced with lots of code examples."--DrDobbs.com, April 2, 2013 "This book belongs on the bookshelf of every HPC professional. Not only does it successfully and accessibly teach us how to use and obtain high performance on the Intel MIC architecture, it is about much more than that. It takes us back to the universal fundamentals of high-performance computing including how to think and reason about the performance of algorithms mapped to modern architectures, and it puts into your hands powerful tools that will be useful for years to come." -Robert J. Harrison, Institute for Advanced Computational Science, Stony Brook University, from the Foreword "The book benefits software engineers, scientific researchers, and high performance and supercomputing developers in need of high-performance computing resources."--HPCwire.com, March 31, 2013 "The book benefits software engineers, scientific researchers, and high performance and supercomputing developers in need of high-performance computing resources.I got my hands on a preliminary copy of the book back in November at SC12, and I can tell you that Jim and James did a great job."--Knowledgespeak.com, April 1, 2013

From the Back Cover

Authors Jim Jeffers and James Reinders spent two years helping educate customers about the prototype and pre-production hardware before Intel introduced the first Intel Xeon Phi coprocessor. They have distilled their own experiences coupled with insights from many expert customers, Intel Field Engineers, Application Engineers and Technical Consulting Engineers, to create this authoritative first book on the essentials of programming for this new architecture and these new products.

This book is useful even before you ever touch a system with an Intel Xeon Phi coprocessor. To ensure that your applications run at maximum efficiency, the authors emphasize key techniques for programming any modern parallel computing system whether based on Intel Xeon processors, Intel Xeon Phi coprocessors, or other high performance microprocessors. Applying these techniques will generally increase your program performance on any system, and better prepare you for Intel Xeon Phi coprocessors and the Intel MIC architecture.

Customer Reviews

3.8 out of 5 stars
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Most Helpful Customer Reviews

Format: Paperback
High performance computing is a vast field, and it makes sense when you have enormously diverse space filled with vastly different solutions - clusters of similar processors, dedicated in-processor vector hardware (such as Intel's AVX) or stand-alone GPGPUs, shared memory, message passing and so on. Writing efficient code for such machines is difficult and writing code that runs well on all kinds is, I dare do say, next to impossible.

The Xeon Phi presents a relatively simple model of homogeneous x86 processors with local vector facilities sharing a pool of memory. This books offers a good intro to HPC and goes into some depths that will help your code perform better on massively multi-core machines.

There was one nagging feeling that kept with me throughout this book. While it's geared towards current HPC problems, several architectural peculiarities of the Xeon Phi also hint towards the only credible future for CPUs. When even phones expose 4-core architectures to their programmers, learning to live with a large collection of relatively low performance cores is a must. While we won't see a Phi-based desktop anytime soon, 4 and 8 core architectures will eventually work their way into low-end machines everybody has. Ignore it at your own peril.
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By Dale Embry on October 20, 2014
Format: Paperback Verified Purchase
good introduction into converting programs to get good performance from any platform, but especially Xeon Phi.
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4 of 9 people found the following review helpful By maikp on September 9, 2013
Format: Paperback
i read the book and figured out that most of the advanced topics
are not covered at all f.e. advanced vectorization using mic-mctp or
hpc async. communication beyond the possibilities of mpi and offloads.
modern pgas approaches are also not in place when it comes to overlapping
of communication and computation. so it is more or less a book for beginners
who have no clue about accelerator programming.
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3 of 11 people found the following review helpful By COSMIC TRAVELER on August 1, 2013
Format: Paperback
Are you a programmer? If you are, then this book is for you! Authors James Jeffers and James Reinders, have done an outstanding job of writing a book that gives you the keys to general parallel programming.

Authors Jeffers and Reinders, begin by Bringing together the essentials to high performance programming for an Intel Xeon Phi coprocessor. Next, they focus on accessing two of the three performance features of the many processing cores with floating point vector processing units and high-speed memory. Then, the authors examine the highly parallel programming with Intel Xeon Phi coprocessors, by using a more substantial yet still relatively simple code example that includes both computation and more complex memory access. They continue by giving an analogy to a real scientific code example that comes from the Riken Advanced Institute for computational Science in Japan. Next, the authors examine the rich set of options available for processors and Intel Xeon Phi coprocessors, with little specific Intel Xeon Phi knowledge required. Then, they show you why you need lots of task level parallelism; and, why you should first consider using OpenMP, Fortran 2008 DO CONCURRENT, Intel Threading Building Blocks, and Intel Cilk Plus. The authors continue by discussing offload models, which have a number of options that blur the distinction a little, specifically _Cilk_Shared; but, still manage distinct task/thread pools on each coprocessor and the host. Next, they examine key elements behind the design of the new Intel computing product line. Then, the authors look at software architecture and components that enable the coprocessor to operate seamlessly in a standard environment.
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Intel Xeon Phi Coprocessor High-Performance Programming
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