Dedicated specifically to the PC interrupt processes, in this guide general interrupt service routines are contrasted with methods of improving the process, including an implied priority chain, an equal priority chain, and an IPC link rotation. Also covered is interrupts using ISA, EISA, PCI, and MCA based PC system boards.
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Most Helpful Customer Reviews
2 of 2 people found the following review helpful:
3.0 out of 5 stars
Needs a revision,
By thatstheticket (Houston, TX USA) - See all my reviews
This review is from: Interrupt Driven PC System Design (Paperback)
This is the only book I've come across that covers the 8259 and compatible PIC's in any significant detail. If you're interrested in interrupt issues on a IA32 system with 8259's then this is a decent book to read side by side with the data sheet from Intel.
Unfortunatly it has a number of flaws. First, the book is written with the assumption that all interrupt code should be able to coexist with existing BIOS, DOS, and Windows 3.1 interrupt code. This boils down to the general assumption, which is out right stated as a fact, that only code that supports Non-Specific EOI's can be used on a "PC System", and as such a number of the 8259's modes of operation can not be used on a "PC System". All statements in bold face that include the words "PC System" should be questioned. Second, it is somewhat repetative between chapters, and between descriptions of the 8259's modes of operation. Third, it does not cover a number of associated topics on interrupt service handling. This steems mainly from the assumption that a "PC System" only runs BIOS, DOS, or Windows 3.1 interrupt code. These topics include the 8259's register access latencies, IO port access and memory synchronization and latency issues on IA32, livelock, and delayed interrupt handling such as in critical sections to name a few. Lastly, it needs a major update. It mentions "string transfers", basicly a rep ins or rep movs instruction sequence, as a "more sophisitcated transfer technique." More likely the section should be updated to include the MMX and SSE instruction sets. Modern systems include APIC's, both Local APIC's and IOAPIC's. These systems further complicate the PC interrupt subsystem because multiple buses may have seperate interrupt controllers thus bluring the destinction between what interrupts can be set as edge triggered, and what interrupts can be set as level triggered. This also changes the effects of the ELCR's. A number of these systems actually report a number of devices that support level trigger mode as edge trigger mode. This changes the notion from "is this device edge or level triggered" to "can I query the device for interrupt request status". Over all, this book does a decent job putting a software oriented perspective on the 8259 which you won't get from reading the Intel data sheet alone. Its unfortunate that certain assumptions are stated as fact thus dating the material covered.
1 of 1 people found the following review helpful:
4.0 out of 5 stars
Instructive, solid, poorly written/edited,
This review is from: Interrupt Driven PC System Design (Paperback)
I'll add more a bit later, but for now I can say that the book deals with all the right stuff, explains exactly what I happen to need at the moment (I bought it a while ago, but got to it only now). A good book overall, and a rare one at that (I don't know of anything equivalent; maybe Messmer's PC hardware book is somewhat similar but not as indepth on that particular topic).
There's, however, one thing that irritates me: the text is extremely poorly written. The quantity of typos, grammatical and useage errors is mind boggling; writing (to nitpick) is awkward at times, redundant and too wordy. The author seems to be trying to really lay it all out (which I appreciate) but he does it ineptly, and frequently makes it actually worse : his repetitive descriptions begin to contradict one another, at least they seem to to me. I would recommend to peruse the interrupts-related sections in the Messmer book first -- if you're comfortable with the basics, McGivern's book will go way more easily. To summarize: The book is fundamentally good and I can wholeheartedly recommend it to anyone who deals with -- or maybe only wants to learn out of general curiosity -- interrupt handling with 8259. Your reading won't be smooth.
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Inside This Book
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First Sentence:
A real time system is one where the success of a process is dependent not only on the accuracy of the computations but also on the timeliness of the results. Read the first page Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
interrupt router, cleanup segment, epc link, rotate procedure, devices using level, interrupt vector byte, interrupt processing hardware, active request signal, link load order, next instruction boundary, interrupt chaining, safety net link, interrupt processing cycle, router assignments, maximum interrupt rate, void interrupt, priority resolver, add starting addresses, sense latch, router modification, second noise signal, vector table address, timer tick count, posted write buffers, ipc link Key Phrases - Capitalized Phrases (CAPs): (learn more)
Nested Slave, Configuration Manager, Locked Slave, Push Registers, Implied Priority Chain, Interrupt Pin, Nested Master, System Resource Manager, Total Service Time, Locked Master, Real Time Clock, Master Pop Registers, Initialization Control Word, Level Control Registers, Bus Number, Local Vector Table, Shared Pulse, Toggle Device, Special Fully Nested Mode, Special Mask Mode, Application Time Base, Configuration Space Header Region, Interrupt Flag, Issuing End of Interrupt, Operational Control Word New!
Books on Related Topics | Concordance | Text Stats Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Index | Back Cover | Surprise Me!
A real time system is one where the success of a process is dependent not only on the accuracy of the computations but also on the timeliness of the results. Read the first page Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
interrupt router, cleanup segment, epc link, rotate procedure, devices using level, interrupt vector byte, interrupt processing hardware, active request signal, link load order, next instruction boundary, interrupt chaining, safety net link, interrupt processing cycle, router assignments, maximum interrupt rate, void interrupt, priority resolver, add starting addresses, sense latch, router modification, second noise signal, vector table address, timer tick count, posted write buffers, ipc link Key Phrases - Capitalized Phrases (CAPs): (learn more)
Nested Slave, Configuration Manager, Locked Slave, Push Registers, Implied Priority Chain, Interrupt Pin, Nested Master, System Resource Manager, Total Service Time, Locked Master, Real Time Clock, Master Pop Registers, Initialization Control Word, Level Control Registers, Bus Number, Local Vector Table, Shared Pulse, Toggle Device, Special Fully Nested Mode, Special Mask Mode, Application Time Base, Configuration Space Header Region, Interrupt Flag, Issuing End of Interrupt, Operational Control Word New!
Books on Related Topics | Concordance | Text Stats Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Index | Back Cover | Surprise Me!
Citations (learn more)
This book cites 6
books:
See all 6 books this book cites
- Inside Out by Rod N. Johnson in Back Matter
- Introduction to Logic Design, Second Edition by Sajjan G. Shiva in Back Matter
- Microcomputers for Engineers and Scientists by Glenn A. Gibson in Back Matter
- Designing with Flash Memory by Brian Dipert in Back Matter
- Fuzzy Logic for Real World Design by Ted Heske in Back Matter
See all 6 books this book cites
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