This book constitutes the thoroughly refereed post-proceedings of the 18th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2005, held in Hawthorne, NY, USA in October 2005. The 26 revised full papers and eight short papers presented were carefully selected during two rounds of reviewing and improvement. The papers are organized in topical sections.
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beacon buffer, reporting thread, fused loop structure, input loop nest, interprocedural ranges, pipelined assembly code, mhp information, path canc, weighted fusion algorithm, classifier learning system, dynamic compilation framework, packet flow analysis, effective cache capacity, escape analysis algorithm, guided empirical search, multigrain parallel processing, visualisation pipeline, speculative children, aligned barriers, stack buffering, test elision, visualisation plan, power saving scheme, abstract threads, array ssa Key Phrases - Capitalized Phrases (CAPs): (learn more)
New York, Springer-Verlag Berlin Heidelberg, Intel Pentium, International Workshop, Parallel Benchmarks, Region Array, University of California, University of Illinois, Intel Itanium, Intel Xeon, Program Generation, Rice University, Computer Society, Base Tiling, David Padua, Very Large Data Bases, Lecture Notes, San Diego, San Francisco, Call Search, Misses Loads Speedup Strategy, Chi-Leung Wong, Codes Base, Frequency Time, Fusion Cycle New!
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beacon buffer, reporting thread, fused loop structure, input loop nest, interprocedural ranges, pipelined assembly code, mhp information, path canc, weighted fusion algorithm, classifier learning system, dynamic compilation framework, packet flow analysis, effective cache capacity, escape analysis algorithm, guided empirical search, multigrain parallel processing, visualisation pipeline, speculative children, aligned barriers, stack buffering, test elision, visualisation plan, power saving scheme, abstract threads, array ssa Key Phrases - Capitalized Phrases (CAPs): (learn more)
New York, Springer-Verlag Berlin Heidelberg, Intel Pentium, International Workshop, Parallel Benchmarks, Region Array, University of California, University of Illinois, Intel Itanium, Intel Xeon, Program Generation, Rice University, Computer Society, Base Tiling, David Padua, Very Large Data Bases, Lecture Notes, San Diego, San Francisco, Call Search, Misses Loads Speedup Strategy, Chi-Leung Wong, Codes Base, Frequency Time, Fusion Cycle New!
Books on Related Topics | Concordance | Text Stats Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Index | Surprise Me!
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