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Leakage in Nanometer CMOS Technologies (Integrated Circuits and Systems)
 
 
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Leakage in Nanometer CMOS Technologies (Integrated Circuits and Systems) [Hardcover]

Siva G. Narendra (Editor), Anantha P. Chandrakasan (Editor)
5.0 out of 5 stars  See all reviews (1 customer review)

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Book Description

0387257373 978-0387257372 November 17, 2005 1
Covers in detail promising solutions at the device, circuit, and architecture levels of abstraction after first explaining the sensitivity of the various MOS leakage sources to these conditions from the first principles. Also treated are the resulting effects so the reader understands the effectiveness of leakage power reduction solutions under these different conditions. Case studies supply real-world examples that reap the benefits of leakage power reduction solutions as the book highlights different device design choices that exist to mitigate increases in the leakage components as technology scales.

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Product Details

  • Hardcover: 317 pages
  • Publisher: Springer; 1 edition (November 17, 2005)
  • Language: English
  • ISBN-10: 0387257373
  • ISBN-13: 978-0387257372
  • Product Dimensions: 9.3 x 6.1 x 0.9 inches
  • Shipping Weight: 1.4 pounds (View shipping rates and policies)
  • Average Customer Review: 5.0 out of 5 stars  See all reviews (1 customer review)
  • Amazon Best Sellers Rank: #2,304,664 in Books (See Top 100 in Books)

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1 of 1 people found the following review helpful:
5.0 out of 5 stars Excellent breadth and depth, March 13, 2006
This review is from: Leakage in Nanometer CMOS Technologies (Integrated Circuits and Systems) (Hardcover)
I am usually a little concerned about edited books. Often they are not coherant. So, I was reluctant to buy this book. But given the topic and some well knownn authors I decided to give it a try. The material is not only cohesive, but also very educational, especially for someone who is new to this area. Right from the introductory material of the first chapter to the detailed methods covered makes this an excellent book for someone who wants to learn about leakage. I foun d the case studies very useful as well.
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Inside This Book (learn more)
First Sentence:
Benefits of CMOS technology scaling in the nanometer regime comes with the disruptive consequence of increasing MOS transistor leakages. Read the first page
Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
power gating, drowsy mode, active leakage reduction, balloon circuit, reverse body bias, sleep transistor, standby voltage scaling, gating transistors, average current method, body bias values, highest frequency bin, intermediate node voltage, power consuming block, standby leakage power, active leakage power, leakage constraint, sleep devices, exclusive discharge patterns, local bias generators, offset source driving, word driver block, body biasing, adaptive body bias, reducing leakage power, standby leakage reduction
Key Phrases - Capitalized Phrases (CAPs): (learn more)
Solid-State Circuits, Test Conf, Circuits Dig, Leakage Dependence, Renesas Microprocessors, International Symposium, Design Automation Conference, Frequency Ratio, Custom Integrated Circuits Conference, Kluwer Academic Publishers, Technologies Figure, Hitachi Ltd, Sequence Design
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