Logic Synthesis and Verification Algorithms [Hardcover]

Gary D. Hachtel (Author), Fabio Somenzi (Author)

Book Description

ISBN-10: 0792397460 | ISBN-13: 978-0792397465 | Publication Date: June 30, 1996 | Edition: 1

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics. A unique feature of this text is the large collection of solved problems. Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.

Editorial Reviews

From the Back Cover

In the last decade logic synthesis has gained widepsread acceptance by designers.  Formal verification is now advancing along the same path.  Computer aided design tools for logic synthesis and verification have become the primary instrument for coping with the ever increasing complexity of designs, and ever more stringent time-to-market constraints.  Effective design must be based on thorough understanding of the capabilities, limitations, and algorithmic principles employed by these tools.  In this book we provide a foundation for such understanding. Logic Synthesis and Verification Algorithms blends mathematical foundations and algorithmic developments with circuit design issues.  Each new technique is presented in the context of its application to design.  Through the study of optimal two-level and multilevel combinational circuit design, the reader is introduced to basic concepts, such as Boolean algebras, local search, and algebraic factorization. Similarly, through the study of optimal sequential circuit design, the reader is introduced to graph algorithms, finite state systems, and language theory.  Throughout the book, recurrent themes such as branch and bound, dynamic programming, and symbolic implicit enumeration are used to establish optimal design principles. Circuit designers and CAD tool developers alike will find Logic Synthesis and Verification Algorithms useful as an introductory and reference text.  The rich collection of examples and solved problems make this book ideal for self study. Because of its careful balance of theory and application, Logic Synthesis and Verification Algorithms will serve well as a textbook for upper division and first year graduate students in electrical and computer engineering. --This text refers to the Paperback edition.

Product Details

• Hardcover: 600 pages
• Publisher: Springer; 1 edition (June 30, 1996)
• Language: English
• ISBN-10: 0792397460
• ISBN-13: 978-0792397465
• Product Dimensions: 10.2 x 7.3 x 1.6 inches
• Shipping Weight: 3.4 pounds
• Average Customer Review: 4.2 out of 5 stars  See all reviews (4 customer reviews)
• Amazon Best Sellers Rank: #587,874 in Books (See Top 100 in Books)

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Customer Reviews

Most Helpful Customer Reviews

2 of 2 people found the following review helpful:

5.0 out of 5 stars exceptional..., July 7, 2004

By A Customer

This review is from: Logic Synthesis and Verification Algorithms (Hardcover)

This book is good. It covers all the fundamentals needed to learn two level and multi level logic synthesis and verification.

It's a good stepping stone for those readers wanting to delve more into the IEEE publications area later on in their careers when implementing new algorithms for logic synthesis.

1 of 1 people found the following review helpful:

3.0 out of 5 stars Good content, poorly written, April 29, 2008

By 

Y. Zhang "yoofor" (College Park, MD USA) - See all my reviews
(REAL NAME)   

This review is from: Logic Synthesis and Verification Algorithms (Paperback)

The book covers most of the fundamental aspects of logic synthesis and verification algorithms commonly implemented in the popular CAD tools. However, the book is poorly written and full of typos. One may constantly wonder what is going on until he reads the material like the 2nd or 3rd times and guess his way through. Sadly, there is rarely a better book in the CAD field, so even though the book is not very well written the material presented is still worth reading especially for any serious readers working in the field of logic synthesis.

5.0 out of 5 stars A well-written exposition and text book, November 29, 2010

By 

Sally100 - See all my reviews

Amazon Verified Purchase

This review is from: Logic Synthesis and Verification Algorithms (Paperback)

This is a very readable book that includes many helpful examples and exercises.
Hachtel's exposition is rigorous and Logic Synthesis and Verification Algorithmscrystal clear.