From the Back Cover
software program for Windows and the Macintosh(TM), fully integrated with LogicWorks 3. With Verilog Modeler, you can create device simulation models using a subset of Verilog, an industry-standard hardware description language. Using Verilog Modeler with LogicWorks 3, students and professionals can learn how to program, design, and test their own circuits. This easy-to-use modeler allows you to modify and debug your Verilog code without switching applications or waiting for long compiles. Simply double-click on a part in the schematic to view or create the Verilog behavioral definition. Variables can be displayed as the simulation progresses, allowing for easy debugging and evaluation. In addition to modeling physical components, LogicWorks Verilog Modeler is ideal for creating stimulus and test programs for other LogicWorks circuits. Features
Fully Integrated Verilog Simulation -- Just double-click on a schematic symbol to create and edit a simulation model.
Interactive Control Panels -- Allow the user to display the internal variables of the Verilog model as the simulation progresses.
Unlimited Execution -- Any number of Verilog models can execute simultaneously in a single design.
Flexible Program Output Options -- Text output from compilation errors, execution errors or $display statements in the source code can be redirected to the screen or to a text file.
Fast Compile Times -- On command, or when you close a source window, Verilog source code is compiled in seconds.
Tool Sharing -- Use LogicWorks Simulation Tools such as the Timing display to create and view simulation data.
