The main focus of this book is to provide the reader with a deep understanding of modeling and design strategies of Current-Mode digital circuits, as well as to organize in a coherent manner all the original and powerful authors’ results in the domain of Current-Mode digital circuits. Model and Design of Bipolar and MOS Current-Mode Logic includes bipolar Current-Mode digital circuits, which emerged as an approach to realize digital circuits with the highest speed, and CMOS Current-Mode digital circuits, which together with its speed performance has been rediscovered to allow logic gates implementations having the feature of low noise level generation. Model and Design of Bipolar and MOS Current-Mode Logic allows the reader not only to understand the operating principle and the features of bipolar and MOS Current-Mode digital circuits, but also to design optimized digital gates. And, although the material is presented in a formal and theoretical manner, much emphasis is devoted to a design perspective. Moreover, to further link the book’s theoretical aspects with practical issues, and to provide the reader with an idea of the real order of magnitude involved assuming actual technologies, numerical examples together with SPICE simulations are included in the book. Model and Design of Bipolar and MOS Current-Mode Logic can be used as a reference to practicing engineers working in this area and as text book to senior undergraduate, graduate and postgraduate students (already familiar with electronic circuits and logic gates) who want to extend their knowledge and cover all aspects of the analysis and design of Current-Mode digital circuits.
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Inside This Book
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Key Phrases - Statistically Improbable Phrases (SIPs):
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npn network, bias current reduction, minimum delay achievable, equivalent linear circuit, unitary transistors, logic swing, transistor emitter area, load capacitance values, cascaded gates, gate topology, assigned bias, delay dependence, input rise time, differential gates, practical design cases, time constant method, bipolar gates, bias current values, buffer bias, latch delay, buffer transistors, simulated delay, static frequency divider, emitter coupled pair, upper transistors Key Phrases - Capitalized Phrases (CAPs): (learn more)
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npn network, bias current reduction, minimum delay achievable, equivalent linear circuit, unitary transistors, logic swing, transistor emitter area, load capacitance values, cascaded gates, gate topology, assigned bias, delay dependence, input rise time, differential gates, practical design cases, time constant method, bipolar gates, bias current values, buffer bias, latch delay, buffer transistors, simulated delay, static frequency divider, emitter coupled pair, upper transistors Key Phrases - Capitalized Phrases (CAPs): (learn more)
Current-Alode Logic New!
Books on Related Topics | Concordance | Text Stats Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Back Cover | Surprise Me!
Citations (learn more)
This book cites 10
books:
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- Microelectronic Circuits: includes CD-ROM (Oxford Series in Electrical and Computer Engineering) by Adel S. Sedra in Back Matter
- Physics of Semiconductor Devices by Simon M. Sze in Back Matter
- Analog Integrated Circuit Design by David Johns in Back Matter
- Semiconductor Devices: Solutions Manual: Physics and Technology by Simon M. Sze in Back Matter
- Design of High-Performance Microprocessor Circuits by Anantha Chandrakasan in Back Matter
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