One of the grand challenges in the nano-scopic computing era is guarantees of robustness. Robust computing system design is confronted with quantum physical, probabilistic, and even biological phenomena, and guaranteeing high reliability is much more difficult than ever before. Scaling devices down to the level of single electron operation will bring forth new challenges due to probabilistic effects and uncertainty in guaranteeing 'zero-one' based computing. Minuscule devices imply billions of devices on a single chip, which may help mitigate the challenge of uncertainty by replication and redundancy. However, such device densities will create a design and validation nightmare with the shear scale. The questions that confront computer engineers regarding the current status of nanocomputing material and the reliability of systems built from such miniscule devices, are difficult to articulate and answer. We have found a lack of resources in the confines of a single volume that at least partially attempts to answer these questions. We believe that this volume contains a large amount of research material as well as new ideas that will be very useful for some one starting research in the arena of nanocomputing, not at the device level, but the problems one would face at system level design and validation when nanoscopic physicality will be present at the device level.
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"This book will serve a unique purpose. Several times over the past few years I have had students ask me to point them toward literature references on defect tolerant architectures for nano-electronics, or nanoelectronics design concepts, etc. For quantum computing and neural nets, well established research communities exist and such references are easy to point to. For some of these other paradigms, papers often appear in journals that biologists, chemists, materials scientists, physicists, etc., rarely encounter - or, worse yet - students must turn to patent literature! This book brings together, for the first time, many of these modern architectural concepts into a single text, with chapters written by a terrific group of experts. It is sure to become a mainstay in my group, and I expect that it will be a valuable resource for many years to come." (Jim Heath, Elizabeth W. Gilloon Professor, California Institute of Technology)
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Inside This Book
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Key Phrases - Statistically Improbable Phrases (SIPs):
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gate failure probabilities, gate failure probability, clocking zone, nanoscale computation, clique energy, clocking level, defect tolerant architectures, logic block level, unbounded model checking, logic margins, restorative stages, nano architectures, thermal energy levels, reconfigurable fabrics, probabilistic model checking, nanoscale wires, quantum hits, majority gate, defect tolerance, electronic nanotechnology, carbon nanotube transistors, zone placement, kink energy, defect map, address wires Key Phrases - Capitalized Phrases (CAPs): (learn more)
Law of Large Numbers, International Conference, Numbers System Design, Device Considerations, New York, Unreliable Nano Devices, San Jose, Computer Society Press, Cambridge University Press, Computer Aided Design, Custom Computing Machines, Design Automation Conference, Prentice Hall, Stanley Williams, Verification of Large Scale Nano Systems, Virginia Tech, Case Study, John von Neumann, Journal of Solid State Circuits, Michael Caffrey, Napa Valley, Notre Dame, Paul Graham, Annual International Symposium, Automata Studies New!
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gate failure probabilities, gate failure probability, clocking zone, nanoscale computation, clique energy, clocking level, defect tolerant architectures, logic block level, unbounded model checking, logic margins, restorative stages, nano architectures, thermal energy levels, reconfigurable fabrics, probabilistic model checking, nanoscale wires, quantum hits, majority gate, defect tolerance, electronic nanotechnology, carbon nanotube transistors, zone placement, kink energy, defect map, address wires Key Phrases - Capitalized Phrases (CAPs): (learn more)
Law of Large Numbers, International Conference, Numbers System Design, Device Considerations, New York, Unreliable Nano Devices, San Jose, Computer Society Press, Cambridge University Press, Computer Aided Design, Custom Computing Machines, Design Automation Conference, Prentice Hall, Stanley Williams, Verification of Large Scale Nano Systems, Virginia Tech, Case Study, John von Neumann, Journal of Solid State Circuits, Michael Caffrey, Napa Valley, Notre Dame, Paul Graham, Annual International Symposium, Automata Studies New!
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Front Cover | Table of Contents | First Pages | Back Cover | Surprise Me!
Citations (learn more)
This book cites 19
books:
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book
cites this book:
- Model Checking by Edmund M. Clarke Jr. in Back Matter (1), and Back Matter (2)
- Digital Integrated Circuits (2nd Edition) by Jan M. Rabaey on page 293, and page 317
- International Conference on Computer Aided Design (Iccad 93) by Institute of Electrical and Electronics Engineers on page 63, and page 100
- Automata Studies. (AM-34) (Annals of Mathematics Studies) by C. E. Shannon on page 67, and page 240
- Symbolic Model Checking by Kenneth L. McMillan in Back Matter (1), and Back Matter (2)
See all 19 books this book cites
- Decision Diagram Techniques for Micro- and Nanoelectronic Design Handbook by Svetlana N. Yanushkevich on page 881
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