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Parallel Computer Organization and Design Hardcover

ISBN-13: 978-0521886758 ISBN-10: 0521886759

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Parallel Computer Organization and Design + Modern Processor Design: Fundamentals of Superscalar Processors + Computer Architecture, Fifth Edition: A Quantitative Approach (The Morgan Kaufmann Series in Computer Architecture and Design)
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Product Details

  • Hardcover: 560 pages
  • Publisher: Cambridge University Press (October 8, 2012)
  • Language: English
  • ISBN-10: 0521886759
  • ISBN-13: 978-0521886758
  • Product Dimensions: 9.8 x 7.3 x 1.2 inches
  • Shipping Weight: 3 pounds (View shipping rates and policies)
  • Average Customer Review: 4.8 out of 5 stars  See all reviews (5 customer reviews)
  • Amazon Best Sellers Rank: #593,648 in Books (See Top 100 in Books)

Editorial Reviews


"Parallel computers and multicore architectures are rapidly gaining importance because the performance of a single core is not improving at the same historical level. Professors Dubois, Annavaram, and Stenstrom have created an easily readable book on the intricacies of parallel architecture design that academicians and practitioners alike will find extremely useful." - Shubu Mukherjee, Cavium, Inc.

"The book can help the readers to understand the principles of parallel systems crystally clear. A necessary book to read for the designers of parallel systems." - Yunji Chen, Institute of Computing Technology, Chinese Academy of Sciences

"All future electronic systems will comprise of a built-in microprocessor, consequently the importance of Computer Architecture will surge. This book provides an excellent tutorial of Computer Architecture fundamentals from the basic technology via processor and memory architecture to chip multiprocessors. I found the book very educationally flow and readable - an excellent instructive book worth using." - Uri Weiser, Technion

"This book really fulfils the need to understand the basic technological on-chip features and constraints in connection with their impact on computer architecture design choices. All computing systems students and developers should first master these single and multi core foundations in a platform independent way, as this comprehensive text does." - Mateo Valero, BSC

"After the drastic shift towards multi-cores that processor architecture has experienced in the past few years, the domain was in dire need of a comprehensive and up-to-date book on the topic. Michel, Murali and Per have crafted an excellent textbook which can serve both as an introduction to multi-core and parallel architectures, as well as a reference for engineers and researchers." - Olivier Temam, INRIA, France

"Parallel Computer Organization and Design" fills an urgent need for a comprehensive and authoritative yet approachable tutorial and reference text for advanced computer architecture topics. All of the key principles and concepts covered in Wisconsin's three-course computer architecture sequence are addressed in a well-organized, thoughtful, and pedagogically appealing manner, without overwhelming the reader with distracting trivia or an excess of quantitative data. In particular, the coverage of chip multiprocessors in Chapter 8 is fully up to date with the state of the art in industry practice, while the final chapter on quantitative evaluation--a true gem!--is a unique and valuable asset that will clearly set this book apart from its competition." - Mikko Lipasti, University of Wisonsin-Madison

"The book contains in-depth coverage of all the aspects of the computer systems. It is comprehensive, systematic, and in sync with the latest development in the field. The skillfully organized book uses self-contained chapters to allow the readers get a complete understanding of a topic without wandering through the whole book. Its content is rich, coherent and clear. Its questions are crafted to stimulate creative thinking. I recommend the book as a must read to all graduate students and young researchers and engineers designing the computers." - Lixin Zhang, Institute of Computing Technology, Chinese Academy of Sciences

"... parallel architectures are the key for high performance and high efficiency computing systems. This book tells the story of parallel architecture at all levels - from the single transistor to the full blown CMP - an unforgettable journey!" - Ronny Ronen, Intel

"Multicore chips have made parallel architectures ubiquitous and their understanding a necessity. This text provides a comprehensive treatment of parallel system architecture and the fundamentals of cache coherence and memory consistency in the most compact form to date. This is a perfect text for a one semester graduate course." - Lawrence Rauchwerger, Texas A&M University

"It is the best of today's books on the subject, and I plan to use it in my class. It is an up-to-date picture of parallel computing that is written in a style that is clear and accessible." - Trevor Mudge, Bredt Family Professor of Computer Engineering, The University of Michigan

"Parallelism, at multiple levels and in many different forms, is now a necessity for all future computer systems, and the new generation of computer scientists and engineers have to master it. To understand the complex interactions among the hundreds of existing ideas, options, and choices, one has to categorize them, put them in order, and then synthesize them. That is precisely what Dubois, Annavaram, and Stenström do, in a magnificent way, in this extremely contemporary and timely book. I want to particularly stress the uniquely clear way in which the authors explain the hardest among these topics: coherence, synchronization, and memory consistency." - Manolis Katevenis, Head of the Computer Architecture and VLSI Systems Laboratory, FORTH-ICS; and Professor of Computer Science, University of Crete, Heraklion, Greece

"This book is a truly comprehensive treatment of parallel computers, from some of the top experts in the field. Well grounded in technology yet remaining very accessible, it also includes important but often overlooked topics such reliability, power, and simulation." - Norm Jouppi, HP

"This text takes a fresh cut at traditional computer architecture topics and considers basic principles from the perspective of multi-core and parallel systems. The need for such a high quality textbook written from this perspective is overdue, and the authors of this text have done a good job in organizing and revamping topics to provide the next generation of computer architects with the basic principles they will need to design multi-core and many-core systems." - David Kaeli, Director of the NU Computer Architecture Research Laboratory, NEU

"An excellent book in an area that has long cried out for tutorial material --- it will be an indispensable resource to students and educators in parallel computer architecture." - Josep Torrellas, University of Illinois

Book Description

Teaching the fundamental design concepts of chip multiprocessors and the challenges of emerging technology, this textbook prepares students for a career designing computer systems of the future. Teeming with practical examples and teachable in a single semester, it is perfect for senior undergraduate and graduate students taking computer architecture courses.

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Most Helpful Customer Reviews

Format: Hardcover Vine Customer Review of Free Product ( What's this? )
It has been clear for some time that barring an overturning of the currently understood laws of physics, the steep increase in the speed of processors with soon start to take on the shape of a horizontal asymptote. As the authors mention, some of the individual components on a chip are now so small that a random cosmic ray contains enough energy to disrupt the operation of the component. This has necessitated the inclusion of shielding to reduce the likelihood of a random ray doing damage.
With this natural limit inevitable, there has been a shift to the simultaneous use of several processors. For many tasks, this can be done as they are essentially distinct jobs. However, the real issue is parallel processing, where the task is dynamically split and segments parceled out for several processors to work on simultaneously. This is easily done for some types of problems, perhaps the best example is when working with large vectors and matrices, for they can be parceled into distinct segments.
The hard problems are those where the processors are required to operate on shared memory locations and the read/write cycles must be coordinated to avoid the potential inaccuracy of race conditions. This requires the inclusion of software locks where other processes cannot access the data until all operations on it are complete.
The authors do an excellent job of presenting the problems of parallel programming as well as many of the current solutions. They open with a brief basic overview of computer architecture and the meaning of parallelism. This is followed by an explanation of the laws of physics that will limit the improvements in the speed of processors.
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2 of 2 people found the following review helpful By L. Wick VINE VOICE on April 19, 2013
Format: Hardcover Vine Customer Review of Free Product ( What's this? )
When I studied parallel computing hardware as a grad student 20+ years ago it was a much simpler field. This turned out to be a perfect book for becoming acquainted with modern design principles and practice. I had a particular need to understand how we can better support database concurrent updates at a hardware level and I got a few nice ideas from the book, in my view way more than the price of admission.
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1 of 1 people found the following review helpful By C.J. Hustwick VINE VOICE on November 25, 2012
Format: Hardcover Vine Customer Review of Free Product ( What's this? )
Like all good intermediate textbooks, this one mixes a conceptual foundations with new material seamlessly. It begins with a review of processor microarchitecture memory hierarchies, proceeds to parallel-programming model abstractions, scalable shared-memory systems; all the way through workload sampling and workload characterization.

Parallel architecture is the answer for the upcoming cap on bandwith execution but it very difficult to design and program. Simple pipelined processor architecture a prerequisite for taking on this subject, but a senior undergraduate student or grad student should find this text straightforward and extremely useful. I can believe it was five years in the making!
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Format: Hardcover
This book puts Patterson/Hennessy's book to shame! (Comp Arch: A Quantitative Approach)

For the most part this book covers everything CA:QA covers while at the same time being much more concrete. Although written by three authors, the book is very well written, greatly organized, sentences are clear and to the point, and most importantly, it does not pointlessly repeat information or put off key topics to the Appendices.

I love the fact that this book covers important information other comp. architecture don't (eg. Gustafson's law, difference between Vector and Array (systolic) processors, CMOS transistor-level basics, message-passing, interconnect basics, routing techniques, programming models). Even more gratifying is the fact that they spend a whole chapter describing the taxonomy of simulators! Every single commercial/academia processor out there is co-designed with the help of simulators nowadays. To me its just mind-boggling that other computer architecture books don't cover this essential topic.

Like any other computer architecture book out there, this book will NOT make you an expert in computer architecture. However, this book does exactly what it is supposed to do, and that is to give you a concise, complete review of what computer architecture is all about.

Having said, I would argue Computer Organization and Design (Hennessy) is a better book for beginners or people that need to review the basics. On the other hand, if you are looking to become more of an expert in any of the subfields within computer architecture I would recommend "Readings in Computer Architecture" by Hill/Jouppi/Sohi. Although not necessary up-to-date, the papers included in that book are classics and definitely must-read.
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Format: Hardcover Vine Customer Review of Free Product ( What's this? )
The book is well suited as a text for a graduate level course in parallel architecture. The authors start with a basic device physics description of the silicon. Describing fundamental properties of the chips, and failure modes like electromigration along a conducting line in the silicon. Power minimisation is broken into 2 parts - for static power and dynamic (AC) power. The leakage current of a transistor in the off mode is often the limiting factor in determining the minimum power loss.

Another chapter then goes into the different types of processor architecture currently built. Here concepts like how to use or rather, maximise, pipelining and the efficacy of branch prediction are discussed. The latter is interesting, in that the text explains how it is implemented in the hardware, and thus outside the control of any software you might load into the CPU.

The technique of Very Long Instruction Word architecture has been around for decades. As we see here, it is still occasionally used. Indeed, the text describes several VLIW implementations.

Another key idea is the use of memory hierarchies. Fast memory caches can or should sit on the same chip as the CPU. The cost of these is simply the cost of the real estate area on the chip. You cannot have a lot of fast caches. But nowadays it is common to have L1, L2 and L3 caches, in order of increasing access time. While off the CPU, there sits main memory, which should be familiar to you, because these are the explicit (if I may use this word) memory chips that are quoted in size whenever you look at the specs of a new computer. Main memory is now several gigabytes, but the problem is that accessing it takes around 200 ns, while getting at the slowed L3 cache is only 20 ns.

The book's strength is that it explains these and other concepts clearly and simply. The narrative gives enough detail for you to appreciate and understand the ideas, without introducing unnecessary clutter.
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