Customer Reviews

A Practical Guide for SystemVerilog Assertions (English and English Edition)

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If you're new to Systemverilog's assertion language (SVA), and want to learn the syntax, this book is for you. The book walks through every major SVA construct (sequence, property, implication operator, repetition operators, etc.), providing detailed examples for each construct.

Unfortunately, some examples are difficult to follow. There is a cycle-based signal-diagram for each example, but the diagram is small, unannotated, and ultimately hard to interpret. (You pretty much have to read the text while jumping back and forth to the diagram.)

Also, the book's coverage of methodology is weak. If you're already know how to write SVA constructs, and are more interested in 'when/where/how' to use SVA, then there are better books out there.

I read VHDLCohen's book for systemverilog assertion but lots of errors in that book. This book is far better for beginners who want to learn how assertion based verification works. It explains SVA with lots of examples.
Really a very good book..