Customer Reviews

Principles of Verifiable RTL Design Second Edition - A Functional Coding Style Supporting Verification Processes in Verilog

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If you are looking for another book describing the Verilog Language Reference Manual then this book is not for you. If, however, to are looking for an excellent set of principles to build a design and verification philosophy then I highly recommend this book. The authors have produced an RTL centric view of design emphasizing the verification process. They argue that synthesis productivity gains have now placed the verification process in the critical path and that equal attention should be giving to coding for verification as is currently given to coding for synthesis. The chapter I particularly enjoyed, entitled "Bad Stuff," provides an excellent discussion with examples on coding styles that hinder efficient verification. The author's discussion of the problems with the use of X at the RT-level, due to X-state pessimism and optimism, and the need for 2-state RTL simulation is enlightening.

The chapter on bad stuff is useful and practical, even though it repeats parts of previous chapters. The chapter on assertion based verification is practical too. Some of the reasonings on use of "x" may be debatable. For example, the authors argued that two-state detects more problems than x injection, based on their experiences. In the text, an example was given. What the example illustrates is NOT the inherent problems with x injection but a truly bad style of coding to detect x. Thus, the example is misleading.

The chapter on formal verification is a cheat-sheet user manual for some commercial tools. It gives a couple of lines of math symbols about formal verification theory, without explanation whatsoever. In general, this chapter is too shallow for understanding the ideas behind formal verification.

In many places, the book just lists the benefits of some practices without giving reasons and details about the practices. It's very frustrating to have the thought hung in mid-air.

So if you are looking for a partial collection of tips to avoid simulation based verification problems, this book is a start. If you want a more in-depth and complete understanding in verifiable RTL design, find other books.

This book presents principles drawn from very large scale designs, like microprocessor. If you are looking for a book describing testbench implementation, another book, "Writing testbenches functional verification of hdl models", is more suitable. If you are working on very large scale and complex design verification, this book will be very helpful. The discussion of simulation optimization, X/Z state, X/Zero/Random initialization during simulation is very insightful.