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Principles of Verifiable RTL Design - A Functional Coding Style Supporting Verification Processes
 
 
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Principles of Verifiable RTL Design - A Functional Coding Style Supporting Verification Processes [Hardcover]

Lionel Bening (Author), Harry D. Foster (Author)
3.7 out of 5 stars  See all reviews (3 customer reviews)

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Principles of Verifiable RTL Design Second Edition - A Functional Coding Style Supporting Verification Processes in Verilog Principles of Verifiable RTL Design Second Edition - A Functional Coding Style Supporting Verification Processes in Verilog 3.7 out of 5 stars (3)
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Book Description

February 29, 2000 0792377885 978-0792377887 1
Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog explains how you can write Verilog to describe chip designs at the RT-level in a manner that cooperates with verification processes. This cooperation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalence checkers. It reduces the labor costs of coverage and formal model checking by facilitating communication between the design engineer and the verification engineer. It also orients the RTL style to provide more useful results from the overall verification process.
The intended audience for Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog is engineers and students who need an introduction to various design verification processes and a supporting functional Verilog RTL coding style. A second intended audience is engineers who have been through introductory training in Verilog and now want to develop good RTL writing practices for verification. A third audience is Verilog language instructors who are using a general text on Verilog as the course textbook but want to enrich their lectures with an emphasis on verification. A fourth audience is engineers with substantial Verilog experience who want to improve their Verilog practice to work better with RTL Verilog verification tools. A fifth audience is design consultants searching for proven verification-centric methodologies. A sixth audience is EDA verification tool implementers who want some suggestions about a minimal Verilog verification subset.
Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog is based on the reality that comes from actual large-scale product design process and tool experience.

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Product Details

  • Hardcover: 272 pages
  • Publisher: Springer; 1 edition (February 29, 2000)
  • Language: English
  • ISBN-10: 0792377885
  • ISBN-13: 978-0792377887
  • Product Dimensions: 9.3 x 6.3 x 0.8 inches
  • Shipping Weight: 1.3 pounds (View shipping rates and policies)
  • Average Customer Review: 3.7 out of 5 stars  See all reviews (3 customer reviews)
  • Amazon Best Sellers Rank: #2,633,384 in Books (See Top 100 in Books)

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11 of 15 people found the following review helpful:
5.0 out of 5 stars Out of the ordinary, April 9, 2000
By 
Jim (Dallas, TX USA) - See all my reviews
This review is from: Principles of Verifiable RTL Design - A Functional Coding Style Supporting Verification Processes (Hardcover)
If you are looking for another book describing the Verilog Language Reference Manual then this book is not for you. If, however, to are looking for an excellent set of principles to build a design and verification philosophy then I highly recommend this book. The authors have produced an RTL centric view of design emphasizing the verification process. They argue that synthesis productivity gains have now placed the verification process in the critical path and that equal attention should be giving to coding for verification as is currently given to coding for synthesis. The chapter I particularly enjoyed, entitled "Bad Stuff," provides an excellent discussion with examples on coding styles that hinder efficient verification. The author's discussion of the problems with the use of X at the RT-level, due to X-state pessimism and optimism, and the need for 2-state RTL simulation is enlightening.
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4 of 5 people found the following review helpful:
1.0 out of 5 stars has practical tips, is shallow in giving understanding, March 18, 2003
By A Customer
The chapter on bad stuff is useful and practical, even though it repeats parts of previous chapters. The chapter on assertion based verification is practical too. Some of the reasonings on use of "x" may be debatable. For example, the authors argued that two-state detects more problems than x injection, based on their experiences. In the text, an example was given. What the example illustrates is NOT the inherent problems with x injection but a truly bad style of coding to detect x. Thus, the example is misleading.

The chapter on formal verification is a cheat-sheet user manual for some commercial tools. It gives a couple of lines of math symbols about formal verification theory, without explanation whatsoever. In general, this chapter is too shallow for understanding the ideas behind formal verification.

In many places, the book just lists the benefits of some practices without giving reasons and details about the practices. It's very frustrating to have the thought hung in mid-air.

So if you are looking for a partial collection of tips to avoid simulation based verification problems, this book is a start. If you want a more in-depth and complete understanding in verifiable RTL design, find other books.

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4 of 5 people found the following review helpful:
5.0 out of 5 stars An excellent book for advanced users, August 7, 2002
This book presents principles drawn from very large scale designs, like microprocessor. If you are looking for a book describing testbench implementation, another book, "Writing testbenches functional verification of hdl models", is more suitable. If you are working on very large scale and complex design verification, this book will be very helpful. The discussion of simulation optimization, X/Z state, X/Zero/Random initialization during simulation is very insightful.
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Inside This Book (learn more)
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First Sentence:
Myriad books, manuals, and articles have addressed the issue of RTL Verilog style with an emphasis on synthesis-oriented policies. Read the first page
Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
verifiable subset, equivalence checking process, bus reversal, assertion monitor library, static timing verifiers, case synthesis directive, combinational logic feedback, casex statements, assertion monitors, procedural blocks, functional verification process, simulation compilers, assertion checkers, specified case statements, formal verification process, targeted library, verification coverage, model checking process, equivalence checker, functional intent, verification confidence, formal equivalence checking, end endmodule, procedural assignments, machine equivalence
Key Phrases - Capitalized Phrases (CAPs): (learn more)
Operator Context Function, Disciplined User Principle, Orthogonal Verification Principle, Functional Observation Principle, Cutpoint Identification Principle, Numeric Value Parameterization Principle, Project Linting Principle, Verifiable Subset Principle, Operator Context Example
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