Real World FPGA Design with Verilog [Paperback]

Ken Coffman (Author)

Book Description

ISBN-10: 0130998516 | ISBN-13: 978-0130998514 | Publication Date: December 18, 1999

The practical guide for every circuit designer creating FPGA designs with Verilog!

Walk through design step-by-step-from coding through silicon. Partitioning, synthesis, simulation, test benches, combinatorial and sequential designs, and more.

Real World FPGA Design with Verilog guides you through every key challenge associated with designing FPGAs and ASICs using Verilog, one of the world's leading hardware design languages. You'll find irreverent, yet rigorous coverage of what it really takes to translate HDL code into hardware-and how to avoid the pitfalls that can occur along the way. Ken Coffman presents no-frills, real-world design techniques that can improve the stability and reliability of virtually any design. Start by walking a typical Verilog design all the way through to silicon; then, review basic Verilog syntax, design; simulation and testing, advanced simulation, and more. Coverage includes:

• Essential digital design strategies: recognizing the underlying analog building blocks used to create digital primitives; implementing logic with LUTs; clocking strategies, logic minimization, and more
• Key engineering tradeoffs, including operating speed vs. latency
• Combinatorial and sequential designs
• Verilog test fixtures: compiler directives and automated testing
• A detailed comparison of alternative architectures and software-including a never-before-published FPGA technology selection checklist

Real World FPGA Design with Verilog introduces libraries and reusable modules, points out opportunities to reuse your own code, and helps you decide when to purchase existing IP designs instead of building from scratch. Essential rules for designing with ASIC conversion in mind are presented.

If you're involved with digital hardware design with Verilog, Ken Coffman is a welcome voice of experience-showing you the shortcuts, helping you over the rough spots, and helping you achieve competence faster than you ever expected!

Editorial Reviews

From the Inside Flap

Preface: Digital Design in the Real World

The world of digital design is changing quickly. At a breathtaking rate, devices are becoming faster, smaller, and denser. Ten years ago the mainstream digital designer was manipulating a few thousand gates using schematics with an occasional ABEL-HDL module tossed into the mix. Now we have programmable devices with a million gates in tiny packages. On the horizon, we see devices with many more millions of gates. It is not practical for the mainstream designer to create systems on chips with schematics (how would you like to deal with a 1,000-page schematic?), so Hardware Description Languages like VHDL and Verilog have come into their own. In spite of strong opinions on both sides of the fence (including my own), the current designscape is bilingual-multilingual if you include the work of those translating C code into hardware and the work of others on more advanced and hybrid languages.

My own opinion of the fundamental reason for Verilog's staying power is that Verilog had a very large head start in the number of engineers who knew Verilog before VHDL really got out of the blocks, and Verilog is easier to learn than VHDL. Thus, the established designers already knew Verilog and had no reason to learn VHDL, and the new designers could pick it up easier than they could pick up VHDL. John Sanguinetti
C2 Design Automation

I always thought that VHDL was the bloated/bureaucratic/design-by-committee deal, and Verilog was the KISS/lean-and-mean/hippy/West Coast approach, and that the usual rules-of-engagement required us to perpetuate and widen the rift between them :)Jonathan Bromley
School of Engineering
Oxford Brookes University
SURVIVAL SKILLS

Regardless of personal opinions, the practical designer will make sure that both VHDL and Verilog skills are present on his or her resume. The current half-life of engineering information is about four years and gets shorter every day. This means that half of what you know today will be obsolete in four years. In order to survive, we weary designers have to do two things:

Master the parts of our skill that are timeless. This includes physics (the analog aspects of digital design, transmission-line theory, conservation of energy, antenna theory, and power management) and design concepts like synchronization, metastability, and propagation delay.

Keep up with the changing technology. Take advantage of free seminars, try to read some of the tidal wave of trade magazines that pile up every month, buy as many books as your Significant Other will tolerate, and pay close attention when smart people are speaking.

80% of all embedded systems are delivered late.Jack Ganssle
The Ganssle GroupThe world of digital design is deeply divided. The elite 10%, the ASIC designers, use hardware and software tools that cost hundreds of thousands of dollars a year to maintain. They earn their living creating specialized high-volume designs. If the FPGA designer uses 50K gates, the ASIC designer uses 500K gates. If the FPGA designer is accustomed to four nanoseconds of delay through a primitive, the ASIC designer is accustomed to delays of less than a nanosecond. The ASIC designer is very careful, methodical, and does extensive planning. Errors can cost hundreds of thousands of dollars in silicon turns and schedule delays. The ASIC designer simulates, simulates, and then simulates some more.By contrast, we FPGA designers are sloppy and impatient. There is little or no cost to experiment, so we program a part and try it. We use tools that are cheap or free on Windows-based PCs. By comparison to ASIC designers, we are a brutish and undisciplined mob, an unruly 90%. I have written this book for those who would like to join me in this mob.

There's also the human element—stress—to the reprogrammability equation. ASICs aren't reprogrammable; the foundry casts their functionality into silicon. Making the final decision to commit a design to an ASIC can be extremely stressful for the entire design team. Once it makes the final decision, the team can't go back without incurring lots more NRE and lots more time. Erring at this stage, thus, is definitely a Career-Limiting Move (CLM). FPGAs, on the other hand, offer engineers a greater comfort zone midway through the project, giving them the ability to go back and revise a design without paying the NRE and time penalties. Reprogrammability alone may well be responsible for much of the success of the FPGA marketplace in the last decade.Rockland K. Awalt
"Making the ASIC/FPGA Decision"
Integrated System Design, July 1999
Reprinted by permission

This is an FPGA synthesis book. It will not make the reader into an ASIC designer, though it does address issues associated with converting an FPGA design to an ASIC. This book is for the newbie FPGA designer who wants a quick and dirty guide to creating FPGA designs that actually stand a chance of surviving in the Real World.

The CD-ROM includes the evaluation version of the Silos III simulator. This software includes a project/file manager, waveform viewer, and full-featured Verilog support. The CD-ROM also includes the demonstration version of David Murray's excellent Prism Editor. This editor includes an automatic commenting/uncommenting feature, smart indentation, color coded Verilog keywords, printing of keywords in bold, column editing, and handling of Verilog code templates. A special price of USD $40.00 was negotiated for purchaser's of this book for those who choose to register the Prism Editor. Also on the CD-ROM is a fully-functional evaluation version of Emath-Pro for Windows, an electronics formula tool with over 300 useful formulas in 19 categories.

I worked hard on this book, but it is not perfect. If you find an error or want to argue about some of the points that are arguable (of which there are many), I look forward to hearing from you.Ken Coffman
Mount Vernon, Washington
kcoffman@sos

From the Back Cover

The practical guide for every circuit designer creating FPGA designs with Verilog!

Walk through design step-by-step-from coding through silicon. Partitioning, synthesis, simulation, test benches, combinatorial and sequential designs, and more.

Real World FPGA Design with Verilog guides you through every key challenge associated with designing FPGAs and ASICs using Verilog, one of the world's leading hardware design languages. You'll find irreverent, yet rigorous coverage of what it really takes to translate HDL code into hardware-and how to avoid the pitfalls that can occur along the way. Ken Coffman presents no-frills, real-world design techniques that can improve the stability and reliability of virtually any design. Start by walking a typical Verilog design all the way through to silicon; then, review basic Verilog syntax, design; simulation and testing, advanced simulation, and more. Coverage includes:

• Essential digital design strategies: recognizing the underlying analog building blocks used to create digital primitives; implementing logic with LUTs; clocking strategies, logic minimization, and more
• Key engineering tradeoffs, including operating speed vs. latency
• Combinatorial and sequential designs
• Verilog test fixtures: compiler directives and automated testing
• A detailed comparison of alternative architectures and software-including a never-before-published FPGA technology selection checklist

Real World FPGA Design with Verilog introduces libraries and reusable modules, points out opportunities to reuse your own code, and helps you decide when to purchase existing IP designs instead of building from scratch. Essential rules for designing with ASIC conversion in mind are presented.

If you're involved with digital hardware design with Verilog, Ken Coffman is a welcome voice of experience-showing you the shortcuts, helping you over the rough spots, and helping you achieve competence faster than you ever expected!

The accompanying CD-ROM contains working demo and student versions of these popular design capture and simulation tools: David Murray's Prism Editor and Simucad's Silos III™ simulator. You also get EMATH (a collection of more than 300 key electrical engineering formulas) and electronic copies of all the Verilog code from this book.

See all Editorial Reviews

Product Details

• Paperback: 291 pages
• Publisher: Prentice Hall (December 18, 1999)
• Language: English
• ISBN-10: 0130998516
• ISBN-13: 978-0130998514
• Product Dimensions: 9.2 x 6.9 x 0.7 inches
• Shipping Weight: 1.8 pounds (View shipping rates and policies)
• Average Customer Review: 3.1 out of 5 stars  See all reviews (12 customer reviews)
• Amazon Best Sellers Rank: #998,018 in Books (See Top 100 in Books)

More About the Author

Ken Coffman was born in Medford, Oregon in 1953. He's been a berry picker, cat food factory worker, dish washer, Air Force Sergeant, rock-n-roll bass player, concert promoter, author, publisher, electrical engineer and engineering manager. In tribute to a life-long love of the written word, he's written nine novels and a technical book. The latest novel is called Fairhaven and it will be released on October 4, 2011. He has two grown children and lives in Washington State with his wife (the futile voice of reason).

Customer Reviews

Most Helpful Customer Reviews

13 of 13 people found the following review helpful:

3.0 out of 5 stars Original approach to Verilog - but needs tune up, August 29, 2000

By 

Avi Chami - See all my reviews

This review is from: Real World FPGA Design with Verilog (Paperback)

When I started reading this book, I was excited about its potential. Written by an engineer, it did not focus on the language, but on real world engineering issues (how about an HDL design book that talks about robustness, metastability, etc. on its first pages?).

The book does address many engineering issues, as well as real FPGA features and constraints that for many engineers take years to learn. Many of this information is there.

But, and it's a big but, the information is not presented clearly. There are too many bugs for a teaching book. And the organization of the text is not good.

Anyway, I would recommend this book to any design engineer interested in learning Verilog (but not as a first book, maybe as a second)

Be sure to pay a visit to this site:

http://www.bytechservices.com/verilog.htm#errata

where there are corrections to the bugs on the book.

About the companion CD: It's a fine piece of CD, with many utilities, of which the Silos Verilog simulator alone almost justifies buying the book itself (btw, you can also download Silos from the Internet)

About myself: I'm a hardware design engineer, with about 10 years experience on the field and the last four years, at HDL design.

10 of 10 people found the following review helpful:

1.0 out of 5 stars Sloppy and incoherent, some useful information, August 15, 2004

By 

D. Brown (Seattle, WA USA) - See all my reviews
(REAL NAME)   

This review is from: Real World FPGA Design with Verilog (Paperback)

This book addresses how to use Verilog to create working FPGA designs. It touches on topics such as clocking, implementation of specific types of logic blocks, and design flow. The examples are written using Verilog.

The writing is sloppy, the organization is incoherent, and the explanations are incomplete. A reader may find the book worthwhile if: he or she already knows most of the material presented, has a few problems that are addressed by the book, can find the discussion of that problem in the book, and the discussion is one of those that is complete and accurate. Otherwise, the book is a waste of time and money.

The author assumes that the reader is familiar with digital logic design, the basics of Verilog, and the basics of FPGA and ASIC design. The book discusses strategies for dealing with practical problems. Unfortunately, the strategies are presented in a disorganized manner, with explanations that are poorly thought out and too incomplete to use.

The first chapter introduces Verilog design for FPGA synthesis. The contents of the chapter are a mish-mash. It is hard to tell what you are supposed to know after reading the chapter that you didn't have to know before reading it. The chapter isn't a quick description of Verilog, because it leaves out most Verilog syntax that you have to know (for example, vectors). The chapter isn't limited to describing what subset of Verilog is synthesizable, because it has detailed but incomplete descriptions of random Verilog topics such as number formats (eg. 1'b0). There are even pages of tables showing boolean logic truth tables for basic logic primitives such as and, or, and xor.

The second chapter is a discussion of how FPGAs are implemented, and the effect that this has on synthesis. For example, clocking strategies are discussed, with some references to differences between FPGAs and ASICs. There is also a discussion of how a logic synthesizer might operate. A few other topics are thrown in, such as a discussion of DeMorgan's theorems. The chapter is too incomplete and poorly-written to be of much practical use. For example, although there is a description of how logic elements can be built out of transistors (including simplified schematics of one possible approach), there is no serious discussion of what implications this has. The book is about FPGA design, but the section on how logic functions are implemented in most FPGAs (as lookup tables) does not describe this in any detail.

The third and fourth chapters, regarding implementing specific digital circuits in FPGAs using Verilog, are potentially the most useful. The concept of the chapters is that they show how to write Verilog for useful functions in a way that can be synthesized well into FPGAs. If the chapters had been well organized and complete, the book would have been worth buying just for them. However, the chapters are as poorly-written as the rest of the book. Large sections are taken up with a discussion of writing adders and subtractors - showing that there is little point in doing so yourself instead of letting the synthesizer do it. However, the discussion of finite state machines - an important topic - covers state machines implemented using binary or Gray codes to represent states. The discussion of 'one-hot' state machines (frequently used in practice in FPGAs) is incomplete, describing only the problems, but failing to present an example that works (or any example at all). Similarly, the discussion of FIFOs (important to synchronize portions of large designs) is limited to a few notes about problems, without a single example. This is surprising, because the book emphasizes that the designer must solve clocking and synchronization problems across large designs, yet solutions to this problem (such as FIFOs) are not described.

The second half of the book, mainly chapters 5 through 8, describe how to use specific Verilog tools. The chapters are useless reiterations of documentation for obsolete versions of specific tools.

Chapter 9, the last chapter, is about designing for ASIC conversion. This could have been a useful chapter, because it covers an important topic.

All in all, I think this is a book to avoid.

On the positive side, this book seems to have fewer obvious editing errors than most other 'instant books'. Also, the typesetting is fairly normal, with reasonable sized text and reasonable margins. The organization and contents of the section headings is hard to understand, but that is a reflection of the disorganization of the book, rather than a problem with the design. The only significant problem I had with the graphic design of the book relates to the graphics, primarily schematics with some screen captures. The scaling is not uniform, so in a single explanation, the size of a schematic symbol and associated label might vary from graphic to graphic. However, this is a minor problem.

14 of 17 people found the following review helpful:

1.0 out of 5 stars Don't waste your money!!!, September 6, 2000

By 

David W. Hawkins (Bishop, CA United States) - See all my reviews

This review is from: Real World FPGA Design with Verilog (Paperback)

I received this book yesterday and read it in about 5 hours - I was very disappointed. in contains a number of typos and several mistakes.

The listing 4-1 on p122 will synthesize a SYNCHRONOUS binary counter, i.e., all DFFs within count_out are clocked simultaneously with the same clk - its inside a process sensitive to clk.

A ripple counter on the other hand has one DFF fed by clk and the other counters are fed by the Q or Q-bar output of the previous FF (where each FF is configured to divide its clock input by two). Often ripple counters are built using T flip-flops. For example,

p594 "Digital Design, Principles and Practices", John Wakerly, 2nd Ed.

pp353-p356 "Fundamentals of digital logic with VHDL design", Brown and Vranesic.

In my opinion, the inclusion of illegible LeonardoSpectrum schematics is a total waste of space. The author could easily have commented on the complexity of the problem in cases where the book formatting would reproduce the schematic poorly. Alternatively, if the author needed the schematic version - redraw it!

For a title that suggests real-world design I was disappointed. The book did contain some annecdotal experience which was interesting, but in terms of how to approach a real-world design with an example of such an approach, I found it lacking.

For example, the only design of any substance in the text is an SRAM controller. However, there is no state diagram or ASM chart showing that the state machine was 'designed' or 'specified' prior to coding, and there are no timing diagrams or test bench to indicate that any simulation of the design was performed, and then there is no final analysis that shows the design met the setup/hold, etc requirements of whatever external SRAM was being used in the design. Those are the real-world issues that the author refers to in the text, but then never does himself.

Also, the HDL pretty-printing is terrible.

Two thumbs down! (I'm sending this book back)