Test Resource Partitioning for System-on-a-Chip (FRONTIERS IN ELECTRONIC TESTING Volume 20) [Hardcover]

Vikram Iyengar (Author), Anshuman Chandra (Author)

Book Description

Publication Date: May 1, 2002 | Series: Frontiers in Electronic Testing (Book 20)

Test Resource Partitioning for System-on-a-Chip is about test resource partitioning and optimization techniques for plug-and-play system-on-a-chip (SOC) test automation. Plug-and-play refers to the paradigm in which core-to-core interfaces as well as core-to-SOC logic interfaces are standardized, such that cores can be easily plugged into "virtual sockets" on the SOC design, and core tests can be plugged into the SOC during test without substantial effort on the part of the system integrator. The goal of the book is to position test resource partitioning in the context of SOC test automation, as well as to generate interest and motivate research on this important topic. SOC integrated circuits composed of embedded cores are now commonplace. Nevertheless, There remain several roadblocks to rapid and efficient system integration. Test development is seen as a major bottleneck in SOC design, and test challenges are a major contributor to the widening gap between design capability and manufacturing capacity. Testing SOCs is especially challenging in the absence of standardized test structures, test automation tools, and test protocols. Test Resource Partitioning for System-on-a-Chip responds to a pressing need for a structured methodology for SOC test automation. It presents new techniques for the partitioning and optimization of the three major SOC test resources: test hardware, testing time and test data volume. Test Resource Partitioning for System-on-a-Chip paves the way for a powerful integrated framework to automate the test flow for a large number of cores in an SOC in a plug-and-play fashion. The framework presented allows the system integrator to reduce test cost and meet short time-to-market requirements.

Product Details

• Hardcover: 248 pages
• Publisher: Springer; 1 edition (May 1, 2002)
• Language: English
• ISBN-10: 1402071191
• ISBN-13: 978-1402071195
• Product Dimensions: 9.6 x 6.4 x 0.8 inches
• Shipping Weight: 1.2 pounds (View shipping rates and policies)
• Average Customer Review: 4.0 out of 5 stars  See all reviews (2 customer reviews)
• Amazon Best Sellers Rank: #4,469,124 in Books (See Top 100 in Books)

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Customer Reviews

Most Helpful Customer Reviews

5.0 out of 5 stars Must-have book for test engineers!, April 30, 2008

By 

Jim Green "Jim" (Dallas, TX) - See all my reviews

This review is from: Test Resource Partitioning for System-on-a-Chip (FRONTIERS IN ELECTRONIC TESTING Volume 20) (Hardcover)

This is a must-have book for test engineers or test software developers in the integrated ckts industry. The book discusses how to optimize test time, tester memory and test hardware. Treatment of complex economics issues is thoughtfully presented. The methods are not patented and can be useful to the average test engineer.

1 of 2 people found the following review helpful:

3.0 out of 5 stars Good book...but not essential, February 20, 2004

By A Customer

This review is from: Test Resource Partitioning for System-on-a-Chip (FRONTIERS IN ELECTRONIC TESTING Volume 20) (Hardcover)

The book is one of a kind in SoC TRP approaches and contains lot of optmization procedures mostly using ILP and MILP..but the whole point if it is just a compendium of papers by the author. Students/ researchers who have access to the digital libraries of ieee/acm/kluwer have no need to purchase the book..I had all the papers and they were interesting and the authors are like the pioneers in the field but the book and the papers are one and the same..so save your money for a different book.