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2 Reviews
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5.0 out of 5 stars
Must-have book for test engineers!,
By Jim Green "Jim" (Dallas, TX) - See all my reviews
This review is from: Test Resource Partitioning for System-on-a-Chip (FRONTIERS IN ELECTRONIC TESTING Volume 20) (Hardcover)
This is a must-have book for test engineers or test software developers in the integrated ckts industry. The book discusses how to optimize test time, tester memory and test hardware. Treatment of complex economics issues is thoughtfully presented. The methods are not patented and can be useful to the average test engineer.
1 of 2 people found the following review helpful:
3.0 out of 5 stars
Good book...but not essential,
By A Customer
This review is from: Test Resource Partitioning for System-on-a-Chip (FRONTIERS IN ELECTRONIC TESTING Volume 20) (Hardcover)
The book is one of a kind in SoC TRP approaches and contains lot of optmization procedures mostly using ILP and MILP..but the whole point if it is just a compendium of papers by the author. Students/ researchers who have access to the digital libraries of ieee/acm/kluwer have no need to purchase the book..I had all the papers and they were interesting and the authors are like the pioneers in the field but the book and the papers are one and the same..so save your money for a different book.
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Test Resource Partitioning for System-on-a-Chip (FRONTIERS IN ELECTRONIC TESTING Volume 20) by Krishnendu Chakrabarty (Hardcover - May 1, 2002)
$129.00
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