Reuse Methodology Manual for System-On-A-Chip Designs [Hardcover]

Michael Keating (Author), Pierre Bricaud (Author)

Book Description

ISBN-10: 0792381750 | ISBN-13: 978-0792381754 | Publication Date: June 30, 1998 | Edition: 1

Silicon technology now allows us to build chips consisting of tens of millions of transistors. This technology promises new levels of system integration onto a single chip, but also presents significant challenges to the chip designer. As a result, many ASIC developers and silicon vendors are re-examining their design methodologies, searching for ways to make effective use of the huge numbers of gates now available.
These designers see current design tools and methodologies as inadequate for developing million-gate ASICs from scratch. There is considerable pressure to keep design team size and design schedules constant while design complexities grow. Tools are not providing the productivity gains required to keep pace with the increasing gate counts available from deep submicron technology. Design reuse - the use of pre-designed and pre-verified cores - is the most promising opportunity to bridge the gap between available gate-count and designer productivity.
Reuse Methodology Manual for System-On-A-Chip Designs outlines an effective methodology for creating reusable designs for use in a System-on-a-Chip (SoC) design methodology. Silicon and tool technologies move so quickly that no single methodology can provide a permanent solution to this highly dynamic problem. Instead, this manual is an attempt to capture and incrementally improve on current best practices in the industry, and to give a coherent, integrated view of the design process.
From the Foreword
`Synopsys and Mentor Graphics have joined forces to help make IP reuse a reality. One of the goals of our Design Reuse Partnership is to develop, demonstrate, and document a reuse-based design methodology that works. The Reuse Manual (RMM) is the result of this effort.'
Aart J. de Geus, Synopsys, Inc.
Walden C. Rhines, Mentor Graphics Corporation

Editorial Reviews

From the Back Cover

Features of the Third Edition: UP TO DATE STATE OF THE ART REUSE AS A SOLUTION FOR CIRCUIT DESIGNERS A CHRONICLE OF "BEST PRACTICES" ALL CHAPTERS UPDATED AND REVISED GENERIC GUIDELINES-NON TOOL SPECIFIC EMPHASIS ON HARD IP AND PHYSICAL DESIGN Reuse Methodology Manual for System-on-a-Chip Designs, Third Edition outlines a set of best practices for creating reusable designs for use in a SoC design methodology. These practices are based on the authors' experience in developing reusable designs, as well as the experience of design teams in many companies around the world. Silicon and tool technologies move so quickly that many of the details of design-for-reuse will undoubtedly continue to evolve over time. But the fundamental aspects of the methodology described in this book have become widely adopted and are likely to form the foundation of chip design for some time to come. Development methodology necessarily differs between system designers and processor designers, as well as between DSP developers and chipset developers. However, there is a common set of problems facing everyone who is designing complex chips. In response to these problems, design teams have adopted a block-based design approach that emphasizes design reuse. Reusing macros (sometimes called "cores") that have already been designed and verified helps to address all of the problems above. However, in adopting reuse-based design, design teams have run into a significant problem. Reusing blocks that have not been explicitly designed for reuse has often provided little or no benefit to the team. The effort to integrate a pre-existing block into new designs can become prohibitively high, if the block does not provide the right views, the right documentation, and the right functionality. From this experience, design teams have realized that reuse-based design requires an explicit methodology for developing reusable macros that are easy to integrate into SoC designs. This manual focuses on describing these techniques. --This text refers to the Paperback edition.

Product Details

• Hardcover: 240 pages
• Publisher: Springer; 1 edition (June 30, 1998)
• Language: English
• ISBN-10: 0792381750
• ISBN-13: 978-0792381754
• Product Dimensions: 9.5 x 6.2 x 0.8 inches
• Shipping Weight: 1.2 pounds
• Average Customer Review: 4.2 out of 5 stars  See all reviews (5 customer reviews)
• Amazon Best Sellers Rank: #3,304,637 in Books (See Top 100 in Books)

Customer Reviews

Most Helpful Customer Reviews

14 of 15 people found the following review helpful:

5.0 out of 5 stars Great baseline text for VLSI designers of all stripes, November 2, 1998

By A Customer

This review is from: Reuse Methodology Manual for System-On-A-Chip Designs (Hardcover)

I really liked this book and found its rules and guidelines very useful. Many of the guidelines are common sense, but it is still very appropriate to have them codified in a single textbook. Practitioners of full-custom approaches to IC design will complain that this is an "ASIC" book. It does have some rules that folks from that background will find hard to swallow (eg, no latches, no gated clocks). But 70% of the book is still applicable to full custom design and will result in faster re-use of full custom cores. The book gets off to a fairly wooly start but becomes substantial with the RTL Coding Guidelines chapter. From then on, its really solid stuff. This is a good book for the times. With much discussion of design re-use and transferable intelectual property in the chip industry, it has all the hallmarks of becoming a 'bible' book for IC designers of all stripes.

4 of 5 people found the following review helpful:

5.0 out of 5 stars Recommend it to every designer as a handbook, December 5, 2001

By 

"mississippiabc" (Fremont, CA USA) - See all my reviews

This review is from: Reuse Methodology Manual for System-On-A-Chip Designs (Hardcover)

The guidelines are not difficult to understand, and you may have the pieces here and there. But this book has a broad coverage. I got this book by luck draw at SNUG. Didn't pay attention at first until I read it. Very well organized, very accurate description of the real feelings of doing a real chip. The methodology it talks about is not limited to "reuse". I suggest the auther change the title for next edition.

2 of 3 people found the following review helpful:

5.0 out of 5 stars Very useful in practice, January 31, 2002

By 

Lee, (Taipei, Taiwan) - See all my reviews

This review is from: Reuse Methodology Manual for System-on-a-Chip Designs (Hardcover)

This book pointed out many design problems that I just met before. Designer could avoid many of them by following the guidelines in this book. I think it would help me a lot in my design work. Thanks to the authors.