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Reuse Methodology Manual for System-on-a-Chip Designs Hardcover – June 30, 2002

ISBN-13: 978-1402071416 ISBN-10: 1402071418 Edition: 3rd

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Product Details

  • Hardcover: 292 pages
  • Publisher: Springer; 3rd edition (June 30, 2002)
  • Language: English
  • ISBN-10: 1402071418
  • ISBN-13: 978-1402071416
  • Product Dimensions: 6.1 x 0.8 x 9.2 inches
  • Shipping Weight: 1.4 pounds
  • Average Customer Review: 4.3 out of 5 stars  See all reviews (6 customer reviews)
  • Amazon Best Sellers Rank: #2,790,302 in Books (See Top 100 in Books)

Editorial Reviews

From the Back Cover

Features of the Third Edition:


Reuse Methodology Manual for System-on-a-Chip Designs, Third Edition outlines a set of best practices for creating reusable designs for use in a SoC design methodology. These practices are based on the authors' experience in developing reusable designs, as well as the experience of design teams in many companies around the world. Silicon and tool technologies move so quickly that many of the details of design-for-reuse will undoubtedly continue to evolve over time. But the fundamental aspects of the methodology described in this book have become widely adopted and are likely to form the foundation of chip design for some time to come.

Development methodology necessarily differs between system designers and processor designers, as well as between DSP developers and chipset developers. However, there is a common set of problems facing everyone who is designing complex chips.

In response to these problems, design teams have adopted a block-based design approach that emphasizes design reuse. Reusing macros (sometimes called "cores") that have already been designed and verified helps to address all of the problems above. However, in adopting reuse-based design, design teams have run into a significant problem. Reusing blocks that have not been explicitly designed for reuse has often provided little or no benefit to the team. The effort to integrate a pre-existing block into new designs can become prohibitively high, if the block does not provide the right views, the right documentation, and the right functionality.

From this experience, design teams have realized that reuse-based design requires an explicit methodology for developing reusable macros that are easy to integrate into SoC designs. This manual focuses on describing these techniques.

--This text refers to the Paperback edition.

Customer Reviews

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Most Helpful Customer Reviews

14 of 15 people found the following review helpful By A Customer on November 2, 1998
Format: Hardcover
I really liked this book and found its rules and guidelines very useful. Many of the guidelines are common sense, but it is still very appropriate to have them codified in a single textbook. Practitioners of full-custom approaches to IC design will complain that this is an "ASIC" book. It does have some rules that folks from that background will find hard to swallow (eg, no latches, no gated clocks). But 70% of the book is still applicable to full custom design and will result in faster re-use of full custom cores. The book gets off to a fairly wooly start but becomes substantial with the RTL Coding Guidelines chapter. From then on, its really solid stuff. This is a good book for the times. With much discussion of design re-use and transferable intelectual property in the chip industry, it has all the hallmarks of becoming a 'bible' book for IC designers of all stripes.
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4 of 5 people found the following review helpful By Amazon Customer on December 5, 2001
Format: Hardcover
The guidelines are not difficult to understand, and you may have the pieces here and there. But this book has a broad coverage. I got this book by luck draw at SNUG. Didn't pay attention at first until I read it. Very well organized, very accurate description of the real feelings of doing a real chip. The methodology it talks about is not limited to "reuse". I suggest the auther change the title for next edition.
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Format: Paperback
I an using STARC RTL style design guide with this manual.

I am mapping STARC rules with the contents of follows.
5.2 Basic Coding Practices
5.2.1 General Naming Conventions
5.2.2 Naming Conventions for VITAL Support
5.2.3 State Variable Names
5.2.4 Include Informational Headers in Source Files
5.2.5 Use Comments
5.2.6 Keep Commands on Separate Lines
5.2.7 Line Length
5.2.8 Indentation
5.2.9 Do not use HDL Reserved Words.
5.2.10 Port Ordering
5.2.11 Port Maps and Generic Maps
5.2.12 VHDL Entity, Architecture and Configuration Section
5.2.13 Use functions
5.2.14 Use loops and arrays
5.2.15 use meaningful labels
5.3 Coding for Portability
5.4 Guidelines for Clocks and resets

These are very helpful with us.
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