Customer Reviews

Reuse Methodology Manual for System-On-A-Chip Designs

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4 star:		(0)
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1 star:		(1)

 

 

I really liked this book and found its rules and guidelines very useful. Many of the guidelines are common sense, but it is still very appropriate to have them codified in a single textbook. Practitioners of full-custom approaches to IC design will complain that this is an "ASIC" book. It does have some rules that folks from that background will find hard to swallow (eg, no latches, no gated clocks). But 70% of the book is still applicable to full custom design and will result in faster re-use of full custom cores. The book gets off to a fairly wooly start but becomes substantial with the RTL Coding Guidelines chapter. From then on, its really solid stuff. This is a good book for the times. With much discussion of design re-use and transferable intelectual property in the chip industry, it has all the hallmarks of becoming a 'bible' book for IC designers of all stripes.

The guidelines are not difficult to understand, and you may have the pieces here and there. But this book has a broad coverage. I got this book by luck draw at SNUG. Didn't pay attention at first until I read it. Very well organized, very accurate description of the real feelings of doing a real chip. The methodology it talks about is not limited to "reuse". I suggest the auther change the title for next edition.

This book pointed out many design problems that I just met before. Designer could avoid many of them by following the guidelines in this book. I think it would help me a lot in my design work. Thanks to the authors.

I an using STARC RTL style design guide with this manual.

I am mapping STARC rules with the contents of follows.
5.2 Basic Coding Practices
5.2.1 General Naming Conventions
5.2.2 Naming Conventions for VITAL Support
5.2.3 State Variable Names
5.2.4 Include Informational Headers in Source Files
5.2.5 Use Comments
5.2.6 Keep Commands on Separate Lines
5.2.7 Line Length
5.2.8 Indentation
5.2.9 Do not use HDL Reserved Words.
5.2.10 Port Ordering
5.2.11 Port Maps and Generic Maps
5.2.12 VHDL Entity, Architecture and Configuration Section
5.2.13 Use functions
5.2.14 Use loops and arrays
5.2.15 use meaningful labels
5.3 Coding for Portability
5.4 Guidelines for Clocks and resets

These are very helpful with us.

Don't spend your money on this book, there is a lot of repetive stuff in it. Also, if you already work in the field of ASIC design, you will not learn much in this book, trust me.