This new volume by interconnection expert on solder joints, Johns H. Lau, deals with BGA, CSP, Flip Chips, and other new technologies that underlie the electronics industry's need for smaller, faster products. Naturally, as ever-smaller products are created, the reliability of the solder joints that bind them becomes increasingly crucial. Balancing concepts and practical applications, the authors explain the fundamentals of solder joint reliability and present creative, robust packaging techniques for cost-effective interconnection.
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Book Description
Editorial Reviews
From the Back Cover
The explosive growth of high-density packaging has created a tremendous impact on the electronic assembly and manufacturing industry. Ball grid array (BGA), chip-scale package (CSP), and solder-bumped flip chip technologies are taking the lead in this advanced manufacturing process. Many major equipment makers and leading electronic companies are now gearing up for these emerging and advanced packaging technologies. For these technologies, solder is the electrical and mechanical "glue," and thus solder joint reliability is one of the most critical issues in the development of these technologies. This book is a one-stop guide to the state of the art of solder joint reliability problem-solving methods, or choose a creative, high-performance, robust, and cost-effective design and high-yield manufacturing process for their interconnect systems will be able to do so with this unique sourcebook. It meets the reference needs of design, material, process, equipment, manufacturing, quality control, product assurance, reliability, component, packaging, vendor, marketing, and system engineers, and technical managers working in electronic packaging and interconnection. This book is structured to provide readers with the necessary know-how for practical, on-the-job problem-solving guidance. The book covers the solder joint reliability of BGA, CSP, flip chip, and FPT assemblies completely, proceeding from the theoretical basics to applications. Specific areas covered include: Definition of reliability, life distribution, failure rate, mean time to failure, etc.; Some well-known life distributions; Accelerated testing; Parameter estimation of life distributions; Acceleration factors for solders; Solder mechanics: plasticity, creep, and constitutive equations; Design, material, and manufacturing processes of BGA, CSP, flip chip, and FTP; Failure analysis and root cause of failure for BGA, CSP, flip chip, and FPT solder joints; Design for reliability of BGA, CSP, flip chip and FPT solder joints; Solder joint reliability of CBGA, PBGA, DBGA, and TBGA assemblies under thermal fatigue, mechanical bending and twisting, and shock and vibration conditions; solder joint reliability of flip chip (e.g., high-temperature and eutectic solder bumped flip chips on ceramic and PCB) assemblies under thermal fatigue, mechanical pulling, shearing, bending and twisting, and shock and vibration conditions; Solder joint reliability of CSP (e.g., LG Semicon's, Mitsubishi's, Motorola's, Tessera's, NEC's, nitto Denko's and Toshiba's) assemblies under thermal fatigue and mechanical bending conditions; Solder joint reliability of PQFP and TSOP assemblies under thermal fatigue, mechanical bending and twisting, and vibration conditions.
About the Author
John H. Lau received his Ph.D. degree in Theoretical and Applied Mechanics from the University of Illinois (1977), a M.A.Sc. degree in Structural Engineering from the University of British Columbia (1973), a second M.S. degree in Engineering Physics from the University of Wisconsin (1974), and a third M.S. degree in Management Science from Fairleigh Dickinson University (1981). He also has a B.E. degree in Civil Engineering from National Taiwan University (1970). John is an interconnection technology scientist at Agilent Technologies, Inc. His current interests cover a broad range of electronic and optoelectronic packaging and manufacturing technology. Prior to Agilent, he worked for Express Packaging Systems, Hewlett-Packard Company, Sandia National Laboratory, Bechtel Power Corporation, and Exxon Production and Research Company. With more than 30 years of R&D and manufacturing experience in the electronics, petroleum, nuclear, and defense industries, he has given over 200 workshops, authored and co-authored over 180 peer reviewed technical publications, and is the author and editor of 13 books: Solder Joint Reliability; Handbook of Tape Automated Bonding; Thermal Stress and Strain in Microelectronics Packaging; The Mechanics of Solder Alloy Interconnects; Handbook of Fine Pitch Surface Mount Technology; Chip On Board Technologies for Multichip Modules; Ball Grid Array Technology; Flip Chip Technologies; Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies; Electronics Packaging: Design, Materials, Process, and Reliability; Chip Scale Package (CSP): Design, Materials, Process, Reliability, and Applications; Low Cost Flip Chip Technologies for DCA, WLCSP, and PBGA Assemblies, and Microvias for Low Cost, High Density Interconnects. John served as one of the associate editors of the IEEE Transactions on Components, Packaging, and Manufacturing Technology and ASME Transactions, Journal of Electronic Packaging. He also served as general chairman, program chairman, and session chairman, and invited speaker of several IEEE, ASME, ASM, MRS, IMAPS, SEMI, and SMI International conferences. He received a few awards from ASME and IEEE for best papers and outstanding technical achievements, and is an ASME Fellow and an IEEE Fellow. He is listed in American Men and Women of Science and Who’s Who in America.
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Inside This Book
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First Sentence:
Figures 1.1 and 1.2 show the trends of IC density (number of transistors per chip) and chip size, respectively. Read the first page Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
cumulative failure point, procurement flow diagram, corner solder joint, leaded solder joints, solder joint reliability, local thermal expansion mismatch, mass reflow processes, plastic shear strain range, global thermal expansion mismatch, flip chip solder joint, eutectic solder balls, eutectic solder bumps, popcorn cracking, underfill epoxy, maximum equivalent plastic strain, thermal fatigue life, cycling test results, chip solder joints, elastoplastic solution, underfill encapsulant, rework conditions, underfill flow, bump diameter, wafer bumping, flip chip bumps Key Phrases - Capitalized Phrases (CAPs): (learn more)
New York, Technology Conference, Van Nostrand Reinhold, Surface Mount Technology, Handbook of Fine Pitch Surface Mount, Journal of Electronic Packaging, Ball Grid Array Technology, International Electronics Manufacturing Technology Symposium, Shear Strain Figure, Circuit World, Multichip Modules, John Wiley, Proceedings of International Symposium, Machine Design, Package Design, Nitto Denko, Pecht Silicone, Chip Scale Package, Winter Annual Meeting, State of the Art, Temperature Constants, Direction of Si Chip Center, Fine Pitch Quad Flat Packs, Journal of Electronic Materials, Las Vegas New!
Books on Related Topics | Concordance | Text Stats Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Index | Back Cover | Surprise Me!
Figures 1.1 and 1.2 show the trends of IC density (number of transistors per chip) and chip size, respectively. Read the first page Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
cumulative failure point, procurement flow diagram, corner solder joint, leaded solder joints, solder joint reliability, local thermal expansion mismatch, mass reflow processes, plastic shear strain range, global thermal expansion mismatch, flip chip solder joint, eutectic solder balls, eutectic solder bumps, popcorn cracking, underfill epoxy, maximum equivalent plastic strain, thermal fatigue life, cycling test results, chip solder joints, elastoplastic solution, underfill encapsulant, rework conditions, underfill flow, bump diameter, wafer bumping, flip chip bumps Key Phrases - Capitalized Phrases (CAPs): (learn more)
New York, Technology Conference, Van Nostrand Reinhold, Surface Mount Technology, Handbook of Fine Pitch Surface Mount, Journal of Electronic Packaging, Ball Grid Array Technology, International Electronics Manufacturing Technology Symposium, Shear Strain Figure, Circuit World, Multichip Modules, John Wiley, Proceedings of International Symposium, Machine Design, Package Design, Nitto Denko, Pecht Silicone, Chip Scale Package, Winter Annual Meeting, State of the Art, Temperature Constants, Direction of Si Chip Center, Fine Pitch Quad Flat Packs, Journal of Electronic Materials, Las Vegas New!
Books on Related Topics | Concordance | Text Stats Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Index | Back Cover | Surprise Me!
Citations (learn more)
This book cites 58
books:
See all 58 books this book cites
- Ball Grid Array Technology by John H. Lau on 7 pages
- Fracture Mechanics (Siam-Ams Proceedings, V. 12.) by N. Y.) Symposium in Applied Mathematics (1978 New York on 5 pages
- Solder Joint Reliability: Theory and applications by John H. Lau on 5 pages
- Flip Chip Technologies by John H. Lau on 4 pages
- Electronic Materials by L.S. Miller in Front Matter, page 88, and page 150
See all 58 books this book cites
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