Static Timing Analysis for Nanometer Designs: A Practical Approach [Hardcover]

J. Bhasker (Author), Rakesh Chadha (Author)

Book Description

ISBN-10: 0387938192 | ISBN-13: 978-0387938196 | Publication Date: April 17, 2009 | Edition: 1

The book covers topics such as cell timing and power modeling; interconnect modeling and analysis, delay calculation, crosstalk, noise and the chip timing verification using static timing analysis. For each of these topics, the book provides a theoretical background as well as detailed examples to elaborate the concepts.

The static timing analysis topics covered start from verification of simple blocks useful for a beginner to this field. The topics then extend to complex nanometer designs with in-depth treatment of concepts such as modeling of on-chip variation, clock gating, half-cycle paths, as well as timing of source-synchronous interfaces such as DDR. The impact of crosstalk on timing and noise is covered as is the usage of hierarchical design methodology.

This book addresses CMOS logic gates, cell library, timing arcs, waveform slew, cell capacitance, timing modeling, interconnect parasitics and coupling, pre- and post-layout interconnect modeling, delay calculation, specification of timing constraints for analysis of internal paths as well as IO interfaces. Advanced modeling and analysis concepts such as controlled current source timing and noise models for nanometer technologies, power modeling including active and leakage power, crosstalk timing and crosstalk glitch calculation, verification of half-cycle and multi-cycle paths, false paths, synchronous interfaces are also covered.

Editorial Reviews

From the Back Cover

Static Timing Analysis for Nanometer Designs: A Practical Approach is a reference for both beginners as well as professionals working in the area of static timing analysis for semiconductors. This book provides a blend of underlying theoretical background and in-depth coverage of timing verification using static timing analysis. The relevant topics such as cell and interconnect modeling, timing calculation, and crosstalk, which can impact the timing of a nanometer design are covered in detail. Timing checks at various process, environment, and interconnect corners, including on-chip variations, are explained in detail. Verification of hierarchal building blocks, full chip, including timing verification of special IO interfaces are covered in detail. Appendices provide complete coverage of SDC, SDF, and SPEF formats. This book is written for professionals working in the area of chip design, timing verification of ASICs and also for graduate students specializing in logic and chip design. Professionals who are beginning to use static timing analysis or are already well-versed in static timing analysis will find this book useful. Static Timing Analysis for Nanometer Designs serves as a reference for a graduate course in chip design and as a text for a course in timing verification for working engineers.

Product Details

• Hardcover: 592 pages
• Publisher: Springer; 1 edition (April 17, 2009)
• Language: English
• ISBN-10: 0387938192
• ISBN-13: 978-0387938196
• Product Dimensions: 9.3 x 6.1 x 1.2 inches
• Shipping Weight: 2.2 pounds (View shipping rates and policies)
• Average Customer Review: 4.0 out of 5 stars  See all reviews (2 customer reviews)
• Amazon Best Sellers Rank: #1,029,731 in Books (See Top 100 in Books)

Customer Reviews

Most Helpful Customer Reviews

4 of 4 people found the following review helpful:

3.0 out of 5 stars good view from the outside; little insight on the insides, May 9, 2010

By 

EE Codewright "Mr.HatMap" (Portland, Oregon USA) - See all my reviews

Amazon Verified Purchase

This review is from: Static Timing Analysis for Nanometer Designs: A Practical Approach (Hardcover)

I'm disappointed with "Static Timing Analysis for Nanometer Designs"
by Bhasker and Chadha, a very expensive book that explains the basics
about static timing analysis, illustrated using a specific tool,
PrimeTime from Synopsys, Inc.

There's little to nothing about how timing analysis itself is done;
for that, try "Timing", by Sachin Sapapnekar. The focus in Bhasker
and Chadha is on constraint modeling, illustrated with the modeling
language SDC, Synopsys Design Constraints.

The physical book is well made and with good quality paper and print.
It is easy on the eyes -- there's lots of white space and timing
diagrams and basic examples, and no obvious typos. And lots and lots
of timing output reports, so many than one's eyes tend to glaze over,
but good to have when you need them. But in too many cases, the
figures are on different pages from the prose describing them, leading
to a lot of page flipping, which impedes learning.

The book is expensive -- it lists for $209.00, and the best price I
found was Amazon's at $165.87. For that kind of money, I want more
insight, more detail, more value. Yet I often felt like I was reading
a user's manual for a tool.

There is a conflict in exposition between simplicity (explain the
basic idea) and complexity (deal with the general case). I'm not a
timing expert, but for a "book [that] can be used as a reference for a
graduate course in chip design" (p. xivv), the exposition stayed quite
rudimentary. Most explanations are predicated on a common clock, and
some issues with setup and hold on multi-cycle paths are not
mentioned; e.g., no mention of the need to check that a multi-cycle
path does not violate setup or hold due to an intermediate clock edge;
I guess it does not occur "in most common scenarios" (page 262).

If you wade and wait long enough though (well more than half way, deep
into chapter 8 "Timing Verification" and into chapter 9 "Interface
Analysis"), you'll be rewarded with descriptions of more complicated
clocking schemes, and an indication of how the setup and hold edges
are determined for non-common clocks.

I was also disappointed with the bibliography -- great books dealing
with circuits and analysis were not mentioned, including "CMOS Circuit
Design, Layout, and Simulation, Revised Second Edition" by R. Jacob
Baker, and "Electronic Circuit and System Simulation Methods" by
Pillage (Pileggi), Rohrer, and Visweswariah.

Is the book clear, does it explain the basics well -- yes. Does the
book address how to *do* static timing analysis, clearly describe the
detailed semantics, or deal with synchronizers and complicated clock
domain crossings -- no. Is it worth the time to read and the money to
acquire -- depends on your needs. I expect it will be helpful; but it
still seems over priced.

[]

1 of 2 people found the following review helpful:

5.0 out of 5 stars a comprehensive primer on static timing analysis concepts, October 14, 2009

By 

Chris Papademetrious "engineer at large" (Saylorsburg, PA United States) - See all my reviews
(REAL NAME)   

This review is from: Static Timing Analysis for Nanometer Designs: A Practical Approach (Hardcover)

When someone enters the world of STA (static timing analysis), it's usually a trial-by-fire where you jump right into the fray and learn as you go. This wasn't too bad several years ago, but STA is complex enough now that this method of learning can be rather painful. Training seminars help convey the basics, but it's hard to absorb months or years worth of practical knowledge in a few days of training.

This book is a great introductory book that covers just about all relevant aspects of STA that an engineer must know. Concepts are explained with lots of reports and timing diagrams, including examples taking from real-world I/O situations (such as DDR interfaces). Timing exceptions, clock gating, crosstalk, clock relationships, static noise - the book provides well-rounded coverage of a broad set of topics which should bring anyone up to a competent level of modern-day STA capability.

Chris Papademetrious
PrimeTime Corporate Applications Engineer
Synopsys Inc.