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Static Timing Analysis for Nanometer Designs: A Practical Approach Hardcover

ISBN-13: 978-0387938196 ISBN-10: 0387938192 Edition: 2009th

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Static Timing Analysis for Nanometer Designs: A Practical Approach + Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC) + An ASIC Low Power Primer: Analysis, Techniques and Specification
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Product Details

  • Hardcover: 572 pages
  • Publisher: Springer; 2009 edition (May 6, 2009)
  • Language: English
  • ISBN-10: 0387938192
  • ISBN-13: 978-0387938196
  • Product Dimensions: 9.3 x 6.4 x 1.6 inches
  • Shipping Weight: 2.2 pounds (View shipping rates and policies)
  • Average Customer Review: 4.5 out of 5 stars  See all reviews (4 customer reviews)
  • Amazon Best Sellers Rank: #749,355 in Books (See Top 100 in Books)

Editorial Reviews

From the Back Cover

Static Timing Analysis for Nanometer Designs: A Practical Approach is a reference for both beginners as well as professionals working in the area of static timing analysis for semiconductors. This book provides a blend of underlying theoretical background and in-depth coverage of timing verification using static timing analysis. The relevant topics such as cell and interconnect modeling, timing calculation, and crosstalk, which can impact the timing of a nanometer design are covered in detail. Timing checks at various process, environment, and interconnect corners, including on-chip variations, are explained in detail. Verification of hierarchal building blocks, full chip, including timing verification of special IO interfaces are covered in detail. Appendices provide complete coverage of SDC, SDF, and SPEF formats.

This book is written for professionals working in the area of chip design, timing verification of ASICs and also for graduate students specializing in logic and chip design. Professionals who are beginning to use static timing analysis or are already well-versed in static timing analysis will find this book useful.

Static Timing Analysis for Nanometer Designs serves as a reference for a graduate course in chip design and as a text for a course in timing verification for working engineers.


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Most Helpful Customer Reviews

7 of 7 people found the following review helpful By EE Codewright on May 9, 2010
Format: Hardcover Verified Purchase
I'm disappointed with "Static Timing Analysis for Nanometer Designs"
by Bhasker and Chadha, a very expensive book that explains the basics
about static timing analysis, illustrated using a specific tool,
PrimeTime from Synopsys, Inc.

There's little to nothing about how timing analysis itself is done;
for that, try "Timing", by Sachin Sapapnekar. The focus in Bhasker
and Chadha is on constraint modeling, illustrated with the modeling
language SDC, Synopsys Design Constraints.

The physical book is well made and with good quality paper and print.
It is easy on the eyes -- there's lots of white space and timing
diagrams and basic examples, and no obvious typos. And lots and lots
of timing output reports, so many than one's eyes tend to glaze over,
but good to have when you need them. But in too many cases, the
figures are on different pages from the prose describing them, leading
to a lot of page flipping, which impedes learning.

The book is expensive -- it lists for $209.00, and the best price I
found was Amazon's at $165.87. For that kind of money, I want more
insight, more detail, more value. Yet I often felt like I was reading
a user's manual for a tool.

There is a conflict in exposition between simplicity (explain the
basic idea) and complexity (deal with the general case). I'm not a
timing expert, but for a "book [that] can be used as a reference for a
graduate course in chip design" (p. xivv), the exposition stayed quite
rudimentary. Most explanations are predicated on a common clock, and
some issues with setup and hold on multi-cycle paths are not
mentioned; e.g.
Read more ›
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By SmithaS on March 5, 2013
Format: Hardcover Verified Purchase
I like how the explanations are very simple and to the point. this is a very good guide for primetime. My only complaint is that the book could have more examples. The book is very good for people who have already used primetime and is not for beginners.
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By Narayan on February 23, 2012
Format: Hardcover Verified Purchase
J Bhasker generally writes easy to understand books. This is another fine example.

This book covers a broad range of topics and is very complete and self contained. This is an excellent refresher on STA and can be used alongside any industry standard tool training one might take. Highly recommended. The price of the book is on the expensive side though.
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1 of 2 people found the following review helpful By Chris Papademetrious on October 14, 2009
Format: Hardcover
When someone enters the world of STA (static timing analysis), it's usually a trial-by-fire where you jump right into the fray and learn as you go. This wasn't too bad several years ago, but STA is complex enough now that this method of learning can be rather painful. Training seminars help convey the basics, but it's hard to absorb months or years worth of practical knowledge in a few days of training.

This book is a great introductory book that covers just about all relevant aspects of STA that an engineer must know. Concepts are explained with lots of reports and timing diagrams, including examples taking from real-world I/O situations (such as DDR interfaces). Timing exceptions, clock gating, crosstalk, clock relationships, static noise - the book provides well-rounded coverage of a broad set of topics which should bring anyone up to a competent level of modern-day STA capability.

Chris Papademetrious
PrimeTime Corporate Applications Engineer
Synopsys Inc.
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