Customer Reviews

Static Timing Analysis for Nanometer Designs: A Practical Approach

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I'm disappointed with "Static Timing Analysis for Nanometer Designs"
by Bhasker and Chadha, a very expensive book that explains the basics
about static timing analysis, illustrated using a specific tool,
PrimeTime from Synopsys, Inc.

There's little to nothing about how timing analysis itself is done;
for that, try "Timing", by Sachin Sapapnekar. The focus in Bhasker
and Chadha is on constraint modeling, illustrated with the modeling
language SDC, Synopsys Design Constraints.

The physical book is well made and with good quality paper and print.
It is easy on the eyes -- there's lots of white space and timing
diagrams and basic examples, and no obvious typos. And lots and lots
of timing output reports, so many than one's eyes tend to glaze over,
but good to have when you need them. But in too many cases, the
figures are on different pages from the prose describing them, leading
to a lot of page flipping, which impedes learning.

The book is expensive -- it lists for $209.00, and the best price I
found was Amazon's at $165.87. For that kind of money, I want more
insight, more detail, more value. Yet I often felt like I was reading
a user's manual for a tool.

There is a conflict in exposition between simplicity (explain the
basic idea) and complexity (deal with the general case). I'm not a
timing expert, but for a "book [that] can be used as a reference for a
graduate course in chip design" (p. xivv), the exposition stayed quite
rudimentary. Most explanations are predicated on a common clock, and
some issues with setup and hold on multi-cycle paths are not
mentioned; e.g., no mention of the need to check that a multi-cycle
path does not violate setup or hold due to an intermediate clock edge;
I guess it does not occur "in most common scenarios" (page 262).

If you wade and wait long enough though (well more than half way, deep
into chapter 8 "Timing Verification" and into chapter 9 "Interface
Analysis"), you'll be rewarded with descriptions of more complicated
clocking schemes, and an indication of how the setup and hold edges
are determined for non-common clocks.

I was also disappointed with the bibliography -- great books dealing
with circuits and analysis were not mentioned, including "CMOS Circuit
Design, Layout, and Simulation, Revised Second Edition" by R. Jacob
Baker, and "Electronic Circuit and System Simulation Methods" by
Pillage (Pileggi), Rohrer, and Visweswariah.

Is the book clear, does it explain the basics well -- yes. Does the
book address how to *do* static timing analysis, clearly describe the
detailed semantics, or deal with synchronizers and complicated clock
domain crossings -- no. Is it worth the time to read and the money to
acquire -- depends on your needs. I expect it will be helpful; but it
still seems over priced.

[]

When someone enters the world of STA (static timing analysis), it's usually a trial-by-fire where you jump right into the fray and learn as you go. This wasn't too bad several years ago, but STA is complex enough now that this method of learning can be rather painful. Training seminars help convey the basics, but it's hard to absorb months or years worth of practical knowledge in a few days of training.

This book is a great introductory book that covers just about all relevant aspects of STA that an engineer must know. Concepts are explained with lots of reports and timing diagrams, including examples taking from real-world I/O situations (such as DDR interfaces). Timing exceptions, clock gating, crosstalk, clock relationships, static noise - the book provides well-rounded coverage of a broad set of topics which should bring anyone up to a competent level of modern-day STA capability.

Chris Papademetrious
PrimeTime Corporate Applications Engineer
Synopsys Inc.