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Step-by-step Functional Verification with SystemVerilog and OVM
 
 
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Step-by-step Functional Verification with SystemVerilog and OVM [Hardcover]

Sasan Iman (Author)
4.4 out of 5 stars  See all reviews (15 customer reviews)


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Book Description

2008

NOTE: Examples in this book can be downloaded from SiMantis Inc. website.

BACK-COVER QUOTES:

"This detailed, step-by-step guide provides a thorough introduction to SystemVerilog and the Open Verification Methodology (OVM). With many examples and clear descriptions, it should be helpful to anyone involved in IC functional verification."

Richard Goering, Editor-in-Chief , SCDsource

 

 "Dr. Iman brings together all the essential elements to understand the use and application of OVM. Those with limited SystemVerilog knowledge will find Step-by-Step Functional Verification with SystemVerilog and OVM offers a complete introduction to SystemVerilog, and the SystemVerilog-savvy will find this a comprehensive OVM reference. This book has everything design and verification engineers would want to know to apply OVM to their most pressing challenges."

Dennis Brophy , Director of Strategic Business Development , Mentor Graphics

 

"The author of this book is well known in the design community as a leader in the verification space. SystemVerilog has provided a major step in our capability to verify our designs, especially in today’s world of 40 million gate SoCs. The combination has produced a very thorough step by step guide to the latest in verification methodology."

Gary Smith, Chief Analyst, Gary Smith EDA

 

"The Open Verification Methodology (OVM) is one of the most quickly and widely adopted new solutions ever for verifying complex chips. This book walks the reader through the OVM as well as the SystemVerilog language constructs upon which it is built. The breadth of Step-by-Step Functional Verification with SystemVerilog and OVM and its pragmatic approach make it an invaluable resource for both novice and experienced verification engineers."

Ted Vucurevich, CTO, Cadence



Product Details

  • Hardcover: 520 pages
  • Publisher: Hansen Brown Publishing (2008)
  • Language: English
  • ISBN-10: 0981656218
  • ISBN-13: 978-0981656212
  • Product Dimensions: 9.3 x 6.3 x 1.1 inches
  • Shipping Weight: 1.9 pounds
  • Average Customer Review: 4.4 out of 5 stars  See all reviews (15 customer reviews)
  • Amazon Best Sellers Rank: #162,177 in Books (See Top 100 in Books)

 

Customer Reviews

15 Reviews
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Average Customer Review
4.4 out of 5 stars (15 customer reviews)
 
 
 
 
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1 of 1 people found the following review helpful:
2.0 out of 5 stars The book is out of date., May 5, 2011
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This review is from: Step-by-step Functional Verification with SystemVerilog and OVM (Hardcover)
The book lays out the verification methodology very well. The problem is that the book was based on OVM 1.0.1. OVM 2.1.1 was the version in use when I bought this book. With this version a lot of the examples in this book are out of date and useless. A good example is chapter 8 which covers sequences it talks about virtual sequencers these have been deprecated, some of the sequence port are gone also. This makes the majority of chapter 8 and later chapters and examples which use virtual sequencer useless. In short the book is too expensive to buy for the information it has in it now. Find a book that has been written more recently.
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1 of 1 people found the following review helpful:
5.0 out of 5 stars A full class-based verification system., March 5, 2009
This review is from: Step-by-step Functional Verification with SystemVerilog and OVM (Hardcover)
Reviewer: José Calero Title: CTO Company: DS2

Book: Step-by-Step Verification Using SystemVerilog and OVM

Finally, a nice to read and straight-forward book that clarifies the basic and advanced concepts behind modern SoC verification and behind the OVM methodology.

Before reading this book, I had the feeling that OVM, although very
powerful, had a painful and long learning curve. This is not anymore the case. The book drives you from the verification basics to the advanced topics, and it does that for both the newcomer and the verification expert willing to know about OVM. In particular, for readers with a previous experience in SoC design, the author introduces the "module-based" approach to verification environments which helps to change-the-mind towards a full class-based verification system.

The book is full with a selected set of example the author uses to describe the topics in a constructive manner (piece of code presented first are used later within examples that describe more complex concepts or complete scenarios). Part 5 of the book, "Environment Implementation and Scenario Generation", wraps-up all the concepts with a complete example.
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1 of 1 people found the following review helpful:
5.0 out of 5 stars Best guide for System VerilogVerilog/OVM, February 13, 2009
This review is from: Step-by-step Functional Verification with SystemVerilog and OVM (Hardcover)
The book is extremely good for any verification engineer. I think it can be very good also for R&D managers to understand better the verification process and flow, in the first chapter the book makes it very clear and well organized.
For junior and senior verificaion engineers the book is very usefull, first to improve and learn verification skills and methodologies, secondly, it explains the system verilog main egines very clear and short with very good examples.
For OVM the book is wonderfull. Since OVM does not have a real specification with examples, this book is the best I found to understand and use OVM in the best and fastest way.
Bottom line, I think it is the best book for OVM that I could find, as well as for engineers that do not have SW programming background in Object Oriented language it explains it very well and clear.
I'm using OVM in my day by day job as a senior verification engneer and this book helped me out in several topics that were not clear for me.
I strongly recomend this book!
Claudiu
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Inside This Book (learn more)
Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
transaction sequences, core utilities, design under verification, verification planning, layered sequences, unidirectional interfaces, virtual sequences, bidirectional interfaces, task runo, virtual sequencer, postponed region, transmit sequencers, sequence item type, abstract evaluation model, layer verification components, data request transfers, random generation engine, clocking event, receive sequencer, verification environment blocks, coverpoint length, design integration step, function newo, sequence generation architecture, ovm field
Key Phrases - Capitalized Phrases (CAPs): (learn more)
Programming Language, Assertion-Based Verification, Verification Scenario Generation, Building the Hierarchy, Verification Environment Architecture, Coverage Collection Engine, Data Modeling, Coverage Design, Building the Verification Plan, Time Figure, Setting the Stage, Constraint-Specific Operators, Verification Environment Component Types, Data Model Views, Sequences Based, System Verilog, Capturing Assertion Requirements, Cross Coverage Elements, Flat Sequences, Simulation Phase Control, Beacon Request, Collection Engine, Port Num
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Front Cover | Table of Contents | First Pages | Index | Back Cover | Surprise Me!
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